Modeling of the Simultaneous Switching Noise in High Speed Electronic Circuit with the Integral Equation Method and Vector Fitting Method

2011 ◽  
Vol 47 (5) ◽  
pp. 1490-1493 ◽  
Author(s):  
Guo-Ping Zou ◽  
Xing-Chang Wei ◽  
Er-Ping Li ◽  
Xiang Cui ◽  
Wei-Dong Zhang
Keyword(s):  
Integral Equation ◽  
High Speed ◽  
Electronic Circuit ◽  
Integral Equation Method ◽  
Equation Method ◽  
Switching Noise ◽  
Vector Fitting ◽  
Fitting Method ◽  
Simultaneous Switching Noise ◽  
Simultaneous Switching

scholarly journals Investigation and Analysis of the Simultaneous Switching Noise in Power Distribution Network with Multi-Power Supplies of High Speed CMOS Circuits

2017 ◽  
Vol 2017 ◽  
pp. 1-10 ◽  
Author(s):  
Khaoula Ait Belaid ◽  
Hassan Belahrach ◽  
Hassan Ayad
Keyword(s):  
Power Distribution ◽  
High Speed ◽  
Electromagnetic Coupling ◽  
Distribution Network ◽  
Switching Noise ◽  
Power Distribution Network ◽  
Vector Fitting ◽  
Rational Function Approximation ◽  
Simultaneous Switching Noise ◽  
Simultaneous Switching

The paper studies a simultaneous switching noise (SSN) in a power distribution network (PDN) with dual supply voltages and two cores. This is achieved by reducing the admittance matrix Y of the PDN then calculating frequency domain impedance with rational function approximation using vector fitting. This paper presents a method of computing the simultaneous switching noise through a switching current, whose properties and details are described. Thus, the results are discussed and performed using MATLAB and PSpice tools. It demonstrated that the presence of many cores in the same PCB influences the SSN due to electromagnetic coupling.

A NOVEL DESIGN METHODOLOGY FOR REDUCING SIMULTANEOUS SWITCHING NOISE EVALUATED BY A DIFFERENTIAL-IBIS STRUCTURE

2010 ◽  
Vol 19 (06) ◽  
pp. 1275-1297
Author(s):  
WEN-TZENG HUANG ◽  
SUN-YEN TAN ◽  
YUAN-JEN CHANG
Keyword(s):  
Integrated Circuit ◽  
High Speed ◽  
Low Voltage ◽  
Switching Noise ◽  
Decoupling Capacitors ◽  
Input Noise ◽  
Low Voltage Operation ◽  
Simultaneous Switching Noise ◽  
Simultaneous Switching ◽  
Ibis Model

Modern electronic products increasingly require high speed, high density, and low-voltage operation. In such designs, the power-delivery system could be affected by input noise to the point that it becomes unstable. Simultaneous switching noise (SSN) is a major factor that interferes with power integrity. Although decoupling capacitors cannot effectively alleviate the problem of SSN, they have been generally used in the HP Simulation Program with Integrated Circuit Emphasis model for reducing SSN. The differential I/O buffer information specification (D-IBIS) model uses equivalent circuits to describe the behavior of an integrated circuit. In this study, we propose a novel method for effectively reducing SSN evaluated by an enhanced D-IBIS model with decoupling capacitors and a high-frequency low-impendence circuit. We show that this new method reduces noise by about 40–64% compared to traditional design methodologies.

Simultaneous Switching Noise Analysis for High-Speed Interface

2009 ◽  
Vol E92-C (4) ◽  
pp. 460-467
Author(s):  
Narimasa TAKAHASHI ◽  
Kenji KAGAWA ◽  
Yutaka HONDA ◽  
Yo TAKAHASHI
Keyword(s):  
High Speed ◽  
Noise Analysis ◽  
Switching Noise ◽  
Simultaneous Switching Noise ◽  
Simultaneous Switching
Sign in / Sign up

Export Citation Format

Share Document