Energy Efficient, Hamming Code Technique for Error Detection/Correction Using In-Memory Computation

2021 ◽  
Author(s):  
Mythrai ◽  
Pragna ◽  
Kavitha S ◽  
P. Singh ◽  
A. P. Shah ◽  
...  
Keyword(s):  
Error Detection ◽  
Energy Efficient ◽  
Hamming Code ◽  
Code Technique

Design and Development of Extended Hamming code technique for SECDAEC in an audio signal

2021 ◽  
Author(s):  
Mallidi Sumalatha ◽  
M. V. Mahesh Babu ◽  
M. L. Sai Teja ◽  
Kamatchi S
Keyword(s):  
Audio Signal ◽  
Hamming Code ◽  
Design And Development ◽  
Code Technique

scholarly journals BIT ERROR DETECTION AND CORRECTION WITH HAMMING CODE ALGORITHM

2017 ◽  
Author(s):  
Robbi Rahim
Keyword(s):  
Error Detection ◽  
Scientific Research ◽  
Hamming Code ◽  
Error Detection And Correction ◽  
Engineering And Technology ◽  
Code Algorithm

This paper has been published in International Journal of Scientific Research in Science, Engineering and Technology (IJSRSET) Volume 3 Issue 1 year of 2017

scholarly journals Lookup Table Algorithm for Error Correction in Color Images

2018 ◽  
Vol 2 (2) ◽  
pp. 63
Author(s):  
Ruaa Alaadeen Abdulsattar ◽  
Nada Hussein M. Ali
Keyword(s):  
Error Correction ◽  
Error Detection ◽  
Color Image ◽  
Color Images ◽  
Lookup Table ◽  
Hamming Code ◽  
Detection Techniques ◽  
Error Ratio ◽  
Error Detection And Correction ◽  
Large Burst

Error correction and error detection techniques are often used in wireless transmission systems. A color image of type BMP is considered as an application of developed lookup table algorithms to detect and correct errors in these images. Decimal Matrix Code (DMC) and Hamming code (HC) techniques were integrated to compose Hybrid Matrix Code (HMC) to maximize the error detection and correction. The results obtained from HMC still have some error not corrected because the redundant bits added by Hamming codes to the data are considered inadequate, and it is suitable when the error rate is low for detection and correction processes. Besides, a Hamming code could not detect large burst error period, in addition, the have same values sometimes which lead to not detect the error and consequently increase the error ratio. The proposed algorithm LUT_CORR is presented to detect and correct errors in color images over noisy channels, the proposed algorithm depends on the parallel Cyclic Redundancy Code (CRC) method that's based on two algorithms: Sarwate and slicing By N algorithms. The LUT-CORR and the aforementioned algorithms were merged to correct errors in color images, the output results correct the corrupted images with a 100 % ratio almost. The above high correction ratio due to some unique values that the LUT-CORR algorithm have. The HMC and the proposed algorithm applied to different BMP images, the obtained results from LUT-CORR are compared to HMC for both Mean Square Error (MSE) and correction ratio.  The outcome from the proposed algorithm shows a good performance and has a high correction ratio to retrieve the source BMP image.

scholarly journals Error Detection and Correction On-Board Nanosatellites Using Hamming Codes

2019 ◽  
Vol 2019 ◽  
pp. 1-15 ◽  
Author(s):  
Caleb Hillier ◽  
Vipin Balyan
Keyword(s):  
Error Correction ◽  
Error Detection ◽  
Simulation Software ◽  
Hamming Code ◽  
Single Event ◽  
Hamming Codes ◽  
Single Event Effects ◽  
Effective Version ◽  
Fast Speed ◽  
Error Detection And Correction

The field of nanosatellites is constantly evolving and growing at a very fast speed. This creates a growing demand for more advanced and reliable EDAC systems that are capable of protecting all memory aspects of satellites. The Hamming code was identified as a suitable EDAC scheme for the prevention of single event effects on-board a nanosatellite in LEO. In this paper, three variations of Hamming codes are tested both in Matlab and VHDL. The most effective version was Hamming [16, 11, 4]2. This code guarantees single-error correction and double-error detection. All developed Hamming codes are suited for FPGA implementation, for which they are tested thoroughly using simulation software and optimized.

scholarly journals Algorithm Level Error Detection in Low Voltage Systolic Array

2021 ◽  
Author(s):  
Mehdi Safarpour
Keyword(s):  
Systolic Array ◽  
Error Detection ◽  
Energy Efficient ◽  
Low Voltage ◽  
Voltage Scaling ◽  
Energy Efficient Architecture ◽  
Algorithm Level

An energy efficient architecture for TPUs that is based on reduced voltage operation. The errors are captured and corrected by utilizing ABFT and hence aggressive voltage scaling is made possible.

scholarly journals FPGA-based redundancy bits reduction algorithm using the enhanced error detection correction code

2018 ◽  
Vol 7 (3) ◽  
pp. 1008 ◽  
Author(s):  
Lean Karlo TOLENTINO ◽  
Maria Victoria PADILLA ◽  
Ronnie SERFA JUAN
Keyword(s):  
Error Detection ◽  
Input Data ◽  
Binary Code ◽  
Transmission Rate ◽  
Deterministic Algorithm ◽  
Reduction Algorithm ◽  
Hamming Code ◽  
Random Errors ◽  
Receiver System ◽  
Original Message

To ensure an error-free transmission in packet switching, additional check bits (either header or a payload) are typically appended to the input data of a message for error detection especially in a string of binary code. Normally, it comes from the input message and as a result of a deterministic algorithm after these data have been processed. The receiver system implements the said algorithm, while the transmitter used it to match the reliability of the sent information and detects whether an error bit has occurred or not. The corrupted bits will be corrected, recovered, and matched with the original message. To further improve the detection and correction of the corrupted transmitted bits, an enhanced error detection correction code implementation was proposed and developed in this paper. This will improve the limitations of using cyclic redundancy checking (CRC) code and Hamming code, by reducing the number of the redundancy bits ‘r’ in CRC due to the needed polynomial generator, and the overhead of interspersing of the r in conventional Hamming code, respectively. Xilinx Spartan 6 (XC7Z020-2CLG4841) FPGA was used to synthesize the proposed enhanced error detection code (EEDC) method. Based on the results, the transmission rate is faster, and an increase in detection of random errors compared with using CRC and Hamming codes.  

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