Assessment of Emerging Graphene based Network-on-chip for Integrated Circuit Design

2021 ◽  
Author(s):  
Yatin Kumar Gupta ◽  
Yash Agrawal ◽  
Rutu Parekh ◽  
Bakul Gohel
Keyword(s):  
Circuit Design ◽  
Integrated Circuit ◽  
Network On Chip ◽  
Integrated Circuit Design ◽  
On Chip

Considerations on the de-embedding of differential devices using two-port techniques

2010 ◽  
Vol 2 (3-4) ◽  
pp. 349-357 ◽  
Author(s):  
Vadim Issakov ◽  
Maciej Wojnowski ◽  
Andreas Thiede ◽  
Robert Weigel
Keyword(s):  
Circuit Design ◽  
Integrated Circuit ◽  
High Frequency ◽  
Mode Conversion ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Integrated Circuit Design ◽  
Differential Signaling ◽  
On Chip

Differential signaling is very common for high frequency integrated circuit design. Accurate multimode de-embedding at multigigahertz frequencies, however, is a major challenge. The differential and common-mode parameters can be obtained by converting the measured four-port nodal S-parameters into the mixed-mode form. Under certain conditions, it is possible to separate the modes and consider only the entries corresponding to the differential S-parameters. This allows to reduce the measured 4 × 4 matrix to a 2 × 2 matrix and consider the differential device as a two-port network. Thus, the standard de-embedding techniques, derived for two-port networks, can be applied to differential S-parameters. The purpose of this paper is to investigate the applicability of this approach for on-wafer measurements. We describe analytically the conditions under which this method is valid. As an example, a 2:1 transformer, manufactured in Infineon's 0.13 μm CMOS (complementary metal-oxide semiconductor) process, has been characterized. On-chip de-embedding structures have been fabricated using the same process. The results obtained using Short-Open, Thru-Line, and Thru-Line-Reflect de-embedding techniques are compared. Additionally, the results are verified by simulation of a device under test having high-mode conversion.

scholarly journals Secure Fault Diagnosis for Framework on Chip Design and Testing

2020 ◽  
Vol 9 (5) ◽  
pp. 715-720
Keyword(s):  
Fault Diagnosis ◽  
Circuit Design ◽  
Integrated Circuit ◽  
Research Paper ◽  
Verilog Hdl ◽  
Integrated Circuit Design ◽  
Chip Design ◽  
Cell Plan ◽  
On Chip ◽  
Design And Testing

Because of the extensive expense of semiconductor fabricating, most framework on-chip structure organizations redistribute their generation to seaward foundries. As a large portion of these gadgets are fabricated in situations of constrained trust that regularly need suitable oversight, various diverse dangers have risen. These incorporate unapproved overabundance of the ICs, offer of out-of-determination/rejected ICs disposed of by assembling tests, robbery of scholarly property, and figuring out of the structures. The Boolean calculations are effectively break keybased confusion techniques and therefore go around the essential destinations of metering and confusion. In this research paper, we present an innovation secure cell plan for executing the structure for-security foundation to avoid releasing the way to a foe under any conditions and produce fault free integrated circuit design. Our proposed structure is impervious to different known assaults at the expense of a next to no region overhead. This Proposed Framework Actualized utilizing Verilog HDL also recreated by Modelsim 6.4 c and Integrated by Xilinx device.

Design of On-Chip Debug System Based on IEEE Protocol

2013 ◽  
Vol 380-384 ◽  
pp. 3115-3117
Author(s):  
Lei Li
Keyword(s):  
Circuit Design ◽  
Integrated Circuit ◽  
Integrated Circuit Design ◽  
Module Design ◽  
Manufacture Process ◽  
Design Idea ◽  
On Chip ◽  
Design And Manufacture

with the integrated circuit design and manufacture process of development of integration complexity rise, chip, chips more and more is also high the testability has become the research difficult and hot problems. At present, according to the design of debugging system pieces is many, but from the module design idea, based on TAP module and debug JTAG with module presents a brand-new debugging system, for our research ideas for reference.

A Case Study of Defects Due to Process-Design Interaction in Nano Scale Technology

2007 ◽  
Author(s):  
Hung-Sung Lin ◽  
Ying-Chin Hou ◽  
Juimei Fu ◽  
Mong-Sheng Wu ◽  
Vincent Huang ◽  
...  
Keyword(s):  
Liquid Crystal ◽  
Circuit Design ◽  
Process Design ◽  
Integrated Circuit ◽  
Photon Emission ◽  
Integrated Circuit Design ◽  
Nano Scale ◽  
Leakage Path ◽  
Related Defect

Abstract The difficulties in identifying the precise defect location and real leakage path is increasing as the integrated circuit design and process have become more and more complicated in nano scale technology node. Most of the defects causing chip leakage are detectable with only one of the FA (Failure Analysis) tools such as LCD (Liquid Crystal Detection) or PEM (Photon Emission Microscope). However, due to marginality of process-design interaction some defects are often not detectable with only one FA tool [1][2]. This paper present an example of an abnormal power consumption process-design interaction related defect which could only be detected with more advanced FA tools.

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