An inductorless piezoelectric energy harvesting interface circuit using gyrator induced voltage flip technique

Purpose The purpose of this research paper is to explore the possibility to enhance the power transfer from piezoelectric energy harvester (PEH) source to the load. As the proposed gyrator-induced voltage flip technique (GIVFT) does not require bulky components such as physical inductors, it is easily realizable in small integrated circuits (IC) package thereby offering performance benefits, reducing area overhead and providing cost benefits for constrained self-powered autonomous Internet-of-Things (IoT) applications. Design/methodology/approach This paper presents an inductorless interface circuit for PEH. The proposed technique is called GIVFT and is demonstrated using active elements. The authors use gyrator to induce voltage flip at the output side of PEH to enhance the charge extraction from PEH. The proposed technique uses the current-voltage (I-V) relationship of gyrator to get appropriate phasor response necessary to induce the voltage flip at the output of PEH to gain power transfer enhancement at the load. Findings The experimental results show the efficacy of the GIVFT realization for enhanced power extraction. The authors have compared their proposed design with popular earlier reported interface circuits. Experimentally measured performance improvement is 1.86×higher than the baseline comparison of full-wave bridge rectifier circuit. The authors demonstrated a voltage flip using GIVFT to gain power transfer improvement in piezoelectric energy harvesting. Originality/value To the best of the authors’ knowledge, pertaining to the field of PEH, this is the first reported GIVFT based on the I-V relationship of the gyrator. The proposed approach could be useful for constrained self-powered autonomous IoT applications, and it could be of importance in guiding the design of new interface circuits for PEH.

Binary-Like Topology Optimization of Piezoelectric Metamaterial Plate with Interface Circuits Using Extended Plane Wave Expansion Method

Piezoelectric metamaterial plate (PMP) is being investigated for structural vibration energy harvesting (SVEH), in which an interface circuit is often used. Thus, it is a challenge to perform bandgap optimization of such an elastic–electro–mechanical coupling system. This paper presents a binary-like topology optimization scheme by dividing the unit cell into identical pieces, where a {0, 1} matrix is optimized to indicate material distribution. Firstly, a unified motion equation is derived for the elastic plate and the piezoelectric patch, and an electromechanical coupling model is built for a self-powered synchronized charge extraction circuit. Then, an extended plane wave expansion method is presented to model the bandgap character of the PMP with interface circuits (PMPICs), and the numerical solution of the dispersion curves is derived based on the Bloch theorem. Next, an extended genetic algorithm is applied for the topology optimization of the PMPIC. In the end, numerical and finite element simulations are performed to validate the proposed method. The results demonstrate that both the structure and the circuit can be optimized simultaneously to obtain the maximum first-order bandgap at a given central frequency. Therefore, the proposed method should provide an effective solution for the topology optimization of a PMPIC for broadband SVEH.

Optimization of spaceflight millimeter-wave impedance matching networks using laser trimming

Realizing packaged state-of-the-art performance of monolithic microwave integrated circuits (MMICs) operating at millimeter wavelengths presents significant challenges in terms of electrical interface circuitry and physical construction. For instance, even with the aid of modern electromagnetic simulation tools, modeling the interaction between the MMIC and its package embedding circuit can lack the necessary precision to achieve optimum device performance. Physical implementation also introduces inaccuracies and requires iterative interface component substitution that can produce variable results, is invasive and risks damaging the MMIC. This paper describes a novel method for in situ optimization of packaged millimeter-wave devices using a pulsed ultraviolet laser to remove pre-selected areas of interface circuit metallization. The method was successfully demonstrated through the optimization of a 183 GHz low noise amplifier destined for use on the MetOp-SG meteorological satellite series. An improvement in amplifier output return loss from an average of 12.9 dB to 22.7 dB was achieved across an operational frequency range of 175–191 GHz and the improved circuit reproduced. We believe that our in situ tuning technique can be applied more widely to planar millimeter-wave interface circuits that are critical in achieving optimum device performance.

Two-Capacitor Direct Interface Circuit for Resistive Sensor Measurements

Direct interface circuits (DICs) avoid the need for signal conditioning circuits and analog-to-digital converters (ADCs) to obtain digital measurements of resistive sensors using only a few passive elements. However, such simple hardware can lead to quantization errors when measuring small resistance values as well as high measurement times and uncertainties for high resistances. Different solutions to some of these problems have been presented in the literature over recent years, although the increased uncertainty in measurements at higher resistance values is a problem that has remained unaddressed. This article presents an economical hardware solution that only requires an extra capacitor to reduce this problem. The circuit is implemented with a field-programmable gate array (FPGA) as a programmable digital device. The new proposal significantly reduces the uncertainty in the time measurements. As a result, the high resistance errors decreased by up to 90%. The circuit requires three capacitor discharge cycles, as is needed in a classic DIC. Therefore, the time to estimate resistance increases slightly, between 2.7% and 4.6%.

New Electronic Interface Circuits for Humidity Measurement Based on the Current Processing Technique

The paper describes a new electronic conditioning circuit based on the current-processing technique for accurate and reliable humidity measurement, without post-processing requirements. Pseudobrookite nanocrystalline (Fe2TiO5) thick film was used as capacitive humidity transducer in the proposed design. The interface integrated circuit was realized in TSMC 0.18 μm CMOS technology, but commercial devices were used for practical realization. The sensing principle of the sensor was obtained by converting the information on environment humidity into a frequency variable square-wave electric current signal. The proposed solution features high linearity, insensitivity to temperature, as well as low power consumption. The sensor has a linear function with relative humidity in the range of Relative Humidity (RH) 30-90 %, error below 1.5 %, and sensitivity 8.3 x 1014 Hz/F evaluated over the full range of changes. A fast recovery without the need of any refreshing methods was observed with a change in RH. The total power dissipation of readout circuitry was 1 mW.