A Noise-shaping SAR Assisted MASH 2-1 Sigma-Delta Modulator

Author(s):  
Yu-Sian Lin ◽  
Soon-Jyh Chang ◽  
Chia-Ling Wei
2019 ◽  
Vol 29 (07) ◽  
pp. 2050108
Author(s):  
Di Li ◽  
Chunlong Fei ◽  
Qidong Zhang ◽  
Yani Li ◽  
Yintang Yang

A high-linearity Multi-stAge noise SHaping (MASH) 2–2–2 sigma–delta modulator (SDM) for 20-MHz signal bandwidth (BW) was presented. Multi-bit quantizers were employed in each stage to provide a sufficiently low quantization noise level and thus improve the signal-to-noise ratio (SNR) performance of the modulator. Mismatch noise in the internal multi-bit digital-to-analog converters (DACs) was analyzed in detail, and an alternative randomization scheme based on multi-layer butterfly-type network was proposed to suppress spurious tones in the output spectrum. Fabricated in a 0.18-[Formula: see text]m single–poly 4-metal Complementary Metal Oxide Semiconductor (CMOS) process, the modulator occupied a chip area of 0.45[Formula: see text]mm2, and dissipated a power of 28.8[Formula: see text]mW from a 1.8-V power supply at a sampling rate of 320[Formula: see text]MHz. The measured spurious-free dynamic range (SFDR) was 94[Formula: see text]dB where 17-dB improvement was achieved by applying the randomizers for multi-bit DACs in the first two stages. The peak signal-to-noise and distortion ratio (SNDR) was 76.9[Formula: see text]dB at [Formula: see text]1 dBFS @ 2.5-MHz input, and the figure-of-merit (FOM) was 126[Formula: see text]pJ/conv.


2013 ◽  
Vol 562-565 ◽  
pp. 311-316
Author(s):  
Xiao Wei Liu ◽  
Qiang Li ◽  
Guan Nan Sun ◽  
Wen Yan Liu

The theory of a Sigma-Delta modulator is introduced in this paper. Based on this theory, a feedback 2-1-1 multi-stage-noise-shaping (MASH) sigma-delta modulator is designed, and the coefficients of the modulator are calculated. The system-level simulation results show that the effective number of bits (ENOB) is 24 bits when the signal bandwidth is 1 kHz and the over-sampling (OSR) rate is 128. Then the circuits of modulator are designed, including integrator, comparator, multi-phase clock and the noise cancelling logic. The whole modulator is simulated in Cadence, the signal to noise ratio (SNR) of the modulator is 125.4dB, and the ENOB is 21.1bits, which meet the technical requirements of the sensor.


2013 ◽  
Vol 22 (09) ◽  
pp. 1340012
Author(s):  
KAREN WAN ◽  
GIGI CHAN ◽  
WILLIAM WONG ◽  
KAM CHUEN WAN ◽  
BRYCE YAU ◽  
...  

A re-configurable switched capacitor sigma-delta analog-to-digital conversion architecture1,2 is proposed. The architecture consists of a MASH sigma delta modulator with nth lower-order (first- or second-order) loops cascaded together. Each loop can be powered on or off operating in high or low performance mode, according to application needs. The architecture can be configured to optimize performance and power consumption for specific resolution and applications. The architecture is proven by means of a prototype, implemented as a fourth-order and fabricated in a standard 0.18 um CMOS technology. The outputs of both high performance mode (fourth-order) and medium performance mode (second-order, first loop ON) are measured to demonstrate the configurability. The FFT demonstrates that the noise shaping for the fourth-order modulator is better than that of the second-order modulator with steeper noise shaping slope.


2013 ◽  
Vol 49 (24) ◽  
pp. 1520-1522
Author(s):  
Wei Chen ◽  
C. Papavassiliou

2000 ◽  
Vol 35 (12) ◽  
pp. 1799-1809 ◽  
Author(s):  
A. Tabatabaei ◽  
B.A. Wooley

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