A 20-MHz BW MASH Sigma–Delta Modulator with Mismatch Noise Randomization for Multi-Bit DACs

2019 ◽  
Vol 29 (07) ◽  
pp. 2050108
Author(s):  
Di Li ◽  
Chunlong Fei ◽  
Qidong Zhang ◽  
Yani Li ◽  
Yintang Yang
Keyword(s):  
Dynamic Range ◽  
Sampling Rate ◽  
Oxide Semiconductor ◽  
Quantization Noise ◽  
Cmos Process ◽  
Noise Shaping ◽  
Signal To Noise ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Chip Area

A high-linearity Multi-stAge noise SHaping (MASH) 2–2–2 sigma–delta modulator (SDM) for 20-MHz signal bandwidth (BW) was presented. Multi-bit quantizers were employed in each stage to provide a sufficiently low quantization noise level and thus improve the signal-to-noise ratio (SNR) performance of the modulator. Mismatch noise in the internal multi-bit digital-to-analog converters (DACs) was analyzed in detail, and an alternative randomization scheme based on multi-layer butterfly-type network was proposed to suppress spurious tones in the output spectrum. Fabricated in a 0.18-[Formula: see text]m single–poly 4-metal Complementary Metal Oxide Semiconductor (CMOS) process, the modulator occupied a chip area of 0.45[Formula: see text]mm2, and dissipated a power of 28.8[Formula: see text]mW from a 1.8-V power supply at a sampling rate of 320[Formula: see text]MHz. The measured spurious-free dynamic range (SFDR) was 94[Formula: see text]dB where 17-dB improvement was achieved by applying the randomizers for multi-bit DACs in the first two stages. The peak signal-to-noise and distortion ratio (SNDR) was 76.9[Formula: see text]dB at [Formula: see text]1 dBFS @ 2.5-MHz input, and the figure-of-merit (FOM) was 126[Formula: see text]pJ/conv.

VCO-BASED CONTINUOUS-TIME SIGMA DELTA ADC BASED ON A DUAL-VCO-QUANTIZER-LOOP STRUCTURE

2013 ◽  
Vol 22 (09) ◽  
pp. 1340013 ◽  
Author(s):  
Z. T. XU ◽  
X. L. ZHANG ◽  
J. Z. CHEN ◽  
S. G. HU ◽  
Q. YU ◽  
...  
Keyword(s):  
Continuous Time ◽  
Signal To Noise Ratio ◽  
Quantization Noise ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Loop Structure ◽  
Signal To Noise ◽  
Sigma Delta ◽  
Analog To Digital ◽  
Sigma Delta Adc

This paper explores a continuous time (CT) sigma delta (ΣΔ) analog-to-digital converter (ADC) based on a dual-voltage-controlled oscillator (VCO)-quantizer-loop structure. A third-order filter is adopted to reduce quantization noise and VCO nonlinearity. Even-order harmonics of VCO are significantly reduced by the proposed dual-VCO-quantizer-loop structure. The prototype with 10 MHz bandwidth and 400 MHz clock rate is designed using a 0.18 μm RF CMOS process. Simulation results show that the signal-to-noise ratio and signal-to-noise distortion ratio (SNDR) are 76.9 and 76 dB, respectively, consuming 37 mA at 1.8 V. The key module of the ADC, which is a 4-bit VCO-based quantizer, can convert the voltage signal into a frequency signal and quantize the corresponding frequency to thermometer codes at 400 MS/s.

scholarly journals A 1.15 μW 200 kS/s 10-b Monotonic SAR ADC Using Dual On-Chip Calibrations and Accuracy Enhancement Techniques

Sensors ◽  
2018 ◽  
Vol 18 (10) ◽  
pp. 3486
Author(s):  
Jae-Hun Lee ◽  
Dasom Park ◽  
Woojin Cho ◽  
Huu Phan ◽  
Cong Nguyen ◽  
...  
Keyword(s):  
Energy Efficient ◽  
Dynamic Range ◽  
Sampling Error ◽  
Sampling Rate ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Calibration Technique ◽  
Accuracy Enhancement ◽  
On Chip ◽  
Comparator Offset

Herein, we present an energy efficient successive-approximation-register (SAR) analog-to-digital converter (ADC) featuring on-chip dual calibration and various accuracy-enhancement techniques. The dual calibration technique is realized in an energy and area-efficient manner for comparator offset calibration (COC) and digital-to-analog converter (DAC) capacitor mismatch calibration. The calibration of common-mode (CM) dependent comparator offset is performed without using separate circuit blocks by reusing the DAC for generating calibration signals. The calibration of the DAC mismatch is efficiently performed by reusing the comparator for delay-based mismatch detection. For accuracy enhancement, we propose new circuit techniques for a comparator, a sampling switch, and a DAC capacitor. An improved dynamic latched comparator is proposed with kick-back suppression and CM dependent offset calibration. An accuracy-enhanced bootstrap sampling switch suppresses the leakage-induced error <180 μV and the sampling error <150 μV. The energy-efficient monotonic switching technique is effectively combined with thermometer coding, which reduces the settling error in the DAC. The ADC is realized using a 0.18 μm complementary metal–oxide–semiconductor (CMOS) process in an area of 0.28 mm2. At the sampling rate fS = 9 kS/s, the proposed ADC achieves a signal-to-noise and distortion ratio (SNDR) of 55.5 dB and a spurious-free dynamic range (SFDR) of 70.6 dB. The proposed dual calibration technique improves the SFDR by 12.7 dB. Consuming 1.15 μW at fS = 200 kS/s, the ADC achieves an SNDR of 55.9 dB and an SFDR of 60.3 dB with a figure-of-merit of 11.4 fJ/conversion-step.

A Novel Dual-Mode Low Pass Sigma-Delta Modulator Chip Design for WCDMA and Bluetooth Applications

2013 ◽  
Vol 660 ◽  
pp. 113-118
Author(s):  
Jhin Fang Huang ◽  
Wen Cheng Lai ◽  
Kun Jie Huang ◽  
Ron Yi Liu
Keyword(s):  
Supply Voltage ◽  
Cmos Process ◽  
Dual Mode ◽  
Chip Design ◽  
Loop Filter ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Chip Area ◽  
Low Pass ◽  
Σδ Modulator

A dual-mode low pass sigma-delta (ΣΔ) modulator at clock rates of 160 and 100 MHz respectively with cascaded integrators is presented for WCDMA and Bluetooth applications. One of main features is that cascaded integrators with feedback as well as distributed input coupling (CIFB) topology erase a summation amplifier and save power consumption. Another feature is that only one set loop filter is designed by switching capacitors to achieve a dual-mode function and greatly saves chip area. A prototype is fabricated in TSMC 0.18-m CMOS process. At the supply voltage of 1.8 V, measured results have achieved the SNDR of 42/33 dB over 1/2 MHz, respectively for Bluetooth/WCDMA. The chip dissipates a low power of 10.5 mW. Including pads the chip area is only 0.61 (0.71× 0.86) mm².

A Performance Prediction Method with an Equation-Based Behavioral Model for a Single-Bit Single-Loop Sigma-Delta Modulator

2012 ◽  
Vol 4 (4) ◽  
pp. 51-69
Author(s):  
Shuenn-Yuh Lee ◽  
Jia-Hua Hong
Keyword(s):  
Dynamic Range ◽  
Behavioral Model ◽  
Cmos Process ◽  
Switched Capacitor ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Single Loop ◽  
The Real ◽  
Switched Capacitor Circuits ◽  
Real Performance

An equation-based behavioral model has been developed to predict the real performance of a single–loop single-bit Sigma Delta Modulator (SDM). By using this prediction flow, not only can the circuit specifications be acquired, including the gain, bandwidth, slew rate of the OPAMPs, and the capacitor value in the switched-capacitor circuits, but the real performance of the SDM can also be predicted. The switched-capacitor circuits according to the required circuit specifications are employed to design a fourth-order feed-forward (FF) SDM with an over-sampling ratio (OSR) of 64 and a bandwidth of 10kHz using a TSMC 0.35µm CMOS process. The measurement results reveal that the SDM with an input frequency of 2.5kHz and a supply voltage of 3.3V can achieve a dynamic range of 90dB and a spurious-free dynamic range (SFDR) of 85dB under the signal bandwidth of 10kHz and a sampling frequency of 1.28MHz, respectively. The precision of the equation-based behavioral model has been validated by experimental measurements, and its inaccuracy is less than 4%.

A High-Resolution Lowpass Sigma-Delta Modulator Applied in Micro-Gyroscope

2014 ◽  
Vol 609-610 ◽  
pp. 964-967
Author(s):  
Jia Jun Zhou ◽  
Di Wang ◽  
Ying Kai Zhao ◽  
Hong Lin Xu ◽  
Xiao Wei Liu
Keyword(s):  
High Resolution ◽  
Dynamic Range ◽  
Sampling Frequency ◽  
Cmos Process ◽  
Effective Number ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
The Stability ◽  
Oversampling Ratio ◽  
Input Level

In this paper, in order to enhance resolution and guarantee the stability of the micro-gyroscope, a high-resolution lowpass sigma-delta modulator is proposed. It employs single-loop fourth-order and full differential structure. The simulated result on the Simulink platform shows that the SNDR is 105.4dB and the effective number of bits (ENOB) is 17.22bits. The entire circuits are implemented with 0.5μm CMOS process. The simulated result on Cadence shows that the SNDR is 99.7dB. The modulator operates at a sampling frequency of 25.6MHz and the signal bandwidth is 100kHz with 128 oversampling ratio (OSR). The dynamic range (DR) is 120 dB approximately and the SNDR changes linearly with the input level.

Architectural Design and Simulation of a Fourth-Order Sigma-Delta Modulator

2014 ◽  
Vol 609-610 ◽  
pp. 723-727
Author(s):  
Wen Jie Fan ◽  
Qiu Ye Lv ◽  
Chong He ◽  
Liang Yin ◽  
Xiao Wei Liu
Keyword(s):  
Fourth Order ◽  
Architectural Design ◽  
Simple Structure ◽  
Dynamic Range ◽  
Sampling Frequency ◽  
System Level ◽  
Noise Shaping ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Sigma Delta Adc

Sigma-delta ADC outperforms the Nyquist ADC in precision and robustness by using oversampling and noise shaping. A fourth-order sigma-delta modulator of input feedforward architecture is designed and simulated in system-level. Input feedforward architecture has advantages of low output swing of integrators and simple structure. Proper circuit parameters are also presented in this paper. The simulation revealed that the modulator achieves 109 dB dynamic range in a signal bandwidth of 1 KHz with a sampling frequency of 250 KHz.

A 16 Bits Sigma-Delta Modulator Applied in Gyroscope

2014 ◽  
Vol 609-610 ◽  
pp. 1077-1081
Author(s):  
Qiang Fu ◽  
Wei Ping Chen ◽  
Ying Kai Zhao ◽  
Liang Yin ◽  
Xiao Wei Liu
Keyword(s):  
Cmos Process ◽  
Noise Shaping ◽  
Effective Number ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Multi Stage ◽  
Ideal Situation ◽  
Sample Frequency ◽  
Sigma Delta Adc ◽  
The Ideal

In this paper, a 4th-order sigma-delta modulator applied in gyroscope is presented. This modulator adopts the 2-1-1 Multi stage noise shaping structure. The bandwidth of signal is 100 KHz, the over sample rate is 64, and sample frequency is 12.8MHz. By the MATLAB Simulink modeling and simulation, when the input signal is 100 KHz, the SNDR of the MASH ADC is 121.8dB, and the effective number of bit is 19.93 in ideal situation. After considering non-ideal factors, the SNDR is 111.6dB, the effective number of bit of ADC is 18.28. Compared with the ideal situation, the noise floor of PSD has increased 40dB. It explains that non-ideal factors have a significant effect on the performance of the sigma-delta ADC. The 4th-order MASH sigma-delta modulator has been implemented under 0.5 um CMOS process and simulated under Cadence. The final simulation results show that SNDR is 112.4 dB and effective number of bits (ENOB) is 18.6.

A Sigma-Delta Modulator System Design with 1-1-1 Mash Structure

2013 ◽  
Vol 389 ◽  
pp. 568-572
Author(s):  
Ming Xin Song ◽  
Zhi Ming Wang ◽  
Yang Yang
Keyword(s):  
Simulation Model ◽  
System Design ◽  
Input Signal ◽  
Dynamic Range ◽  
Gain Coefficient ◽  
Process Conditions ◽  
Cmos Process ◽  
Audio Frequency ◽  
Sigma Delta Modulator ◽  
Sigma Delta

This paper designs a three cascaded sigma-delta modulator with using mash structure. Analysis of gain coefficient of each module and simulate the modulator for the behavioral level. In 0.5μm CMOS process conditions, the input signal bandwidth is 20 kHz, oversampling rate is 256, SNR of the simulation model can get 100.5 dB, and accuracy is greater than 16 bit. Compared with other structures of the modulator, it has more stable and more dynamic range, so it can be applied to audio-frequency circuit.

High Resolution High Power Low Frequency Digital-to-Analog Converter

2010 ◽  
Vol 164 ◽  
pp. 133-138
Author(s):  
Vytenis Puidokas ◽  
Albinas J. Marcinkevičius
Keyword(s):  
Low Frequency ◽  
Quantization Noise ◽  
Transmission Characteristics ◽  
Sigma Delta Modulator ◽  
Digital To Analog Converter ◽  
Sigma Delta ◽  
Chip Area ◽  
Amplitude Frequency Response ◽  
Analog Converter ◽  
Output Filter

The architectural scheme of the designed Sigma-Delta DAC on the FPGA is considered. The place of the interpolator in Sigma-Delta DACs is briefly discussed. The summarized structure of the most common interpolators is presented. More applicable structures of interpolators were suggested and analyzed, providing the comparison with [1]. Having changed the structure of the incomplete interpolator and having optimized the stages, it was possible to improve the characteristic of amplitude frequency response with a smaller number of non-zero coefficients and much lower FPGA resources. The paper provides simulated results of the interpolator filter transmission characteristics as well as Sigma-Delta modulator quantization noise parameters. It is demonstrated that simulation of the complete converter system (interpolator + modulator + output filter) allows to identify places of the interpolator, where hardware resources could be saved, thereby reducing the chip area occupied by the converter, which is not always obvious when analyzing nodes separately. Therefore another version of the interpolator was proposed for the system ensuring larger suppression of the additional frequency band in the whole system compared with the previous interpolator. Simulated results related to occupied chip resources are also confirmed by the experiment, which was implemented in Xilinx Spartan FPGA.

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