Multi stage noise shaping sigma–delta modulator (MASH) for capacitive MEMS accelerometers

2012 ◽  
Vol 186 ◽  
pp. 169-177 ◽  
Author(s):  
Bader Almutairi ◽  
Michael Kraft
Keyword(s):  
Noise Shaping ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Multi Stage ◽  
Mems Accelerometers ◽  
Capacitive Mems

A Fourth-Order MASH Sigma-Delta Modulator in Inertial Sensors

2013 ◽  
Vol 562-565 ◽  
pp. 311-316
Author(s):  
Xiao Wei Liu ◽  
Qiang Li ◽  
Guan Nan Sun ◽  
Wen Yan Liu
Keyword(s):  
Inertial Sensors ◽  
Signal To Noise Ratio ◽  
System Level ◽  
Noise Shaping ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Technical Requirements ◽  
System Level Simulation ◽  
Multi Stage ◽  
Multi Phase

The theory of a Sigma-Delta modulator is introduced in this paper. Based on this theory, a feedback 2-1-1 multi-stage-noise-shaping (MASH) sigma-delta modulator is designed, and the coefficients of the modulator are calculated. The system-level simulation results show that the effective number of bits (ENOB) is 24 bits when the signal bandwidth is 1 kHz and the over-sampling (OSR) rate is 128. Then the circuits of modulator are designed, including integrator, comparator, multi-phase clock and the noise cancelling logic. The whole modulator is simulated in Cadence, the signal to noise ratio (SNR) of the modulator is 125.4dB, and the ENOB is 21.1bits, which meet the technical requirements of the sensor.

A 16 Bits Sigma-Delta Modulator Applied in Gyroscope

2014 ◽  
Vol 609-610 ◽  
pp. 1077-1081
Author(s):  
Qiang Fu ◽  
Wei Ping Chen ◽  
Ying Kai Zhao ◽  
Liang Yin ◽  
Xiao Wei Liu
Keyword(s):  
Cmos Process ◽  
Noise Shaping ◽  
Effective Number ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Multi Stage ◽  
Ideal Situation ◽  
Sample Frequency ◽  
Sigma Delta Adc ◽  
The Ideal

In this paper, a 4th-order sigma-delta modulator applied in gyroscope is presented. This modulator adopts the 2-1-1 Multi stage noise shaping structure. The bandwidth of signal is 100 KHz, the over sample rate is 64, and sample frequency is 12.8MHz. By the MATLAB Simulink modeling and simulation, when the input signal is 100 KHz, the SNDR of the MASH ADC is 121.8dB, and the effective number of bit is 19.93 in ideal situation. After considering non-ideal factors, the SNDR is 111.6dB, the effective number of bit of ADC is 18.28. Compared with the ideal situation, the noise floor of PSD has increased 40dB. It explains that non-ideal factors have a significant effect on the performance of the sigma-delta ADC. The 4th-order MASH sigma-delta modulator has been implemented under 0.5 um CMOS process and simulated under Cadence. The final simulation results show that SNDR is 112.4 dB and effective number of bits (ENOB) is 18.6.

A 20-MHz BW MASH Sigma–Delta Modulator with Mismatch Noise Randomization for Multi-Bit DACs

2019 ◽  
Vol 29 (07) ◽  
pp. 2050108
Author(s):  
Di Li ◽  
Chunlong Fei ◽  
Qidong Zhang ◽  
Yani Li ◽  
Yintang Yang
Keyword(s):  
Dynamic Range ◽  
Sampling Rate ◽  
Oxide Semiconductor ◽  
Quantization Noise ◽  
Cmos Process ◽  
Noise Shaping ◽  
Signal To Noise ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Chip Area

A high-linearity Multi-stAge noise SHaping (MASH) 2–2–2 sigma–delta modulator (SDM) for 20-MHz signal bandwidth (BW) was presented. Multi-bit quantizers were employed in each stage to provide a sufficiently low quantization noise level and thus improve the signal-to-noise ratio (SNR) performance of the modulator. Mismatch noise in the internal multi-bit digital-to-analog converters (DACs) was analyzed in detail, and an alternative randomization scheme based on multi-layer butterfly-type network was proposed to suppress spurious tones in the output spectrum. Fabricated in a 0.18-[Formula: see text]m single–poly 4-metal Complementary Metal Oxide Semiconductor (CMOS) process, the modulator occupied a chip area of 0.45[Formula: see text]mm2, and dissipated a power of 28.8[Formula: see text]mW from a 1.8-V power supply at a sampling rate of 320[Formula: see text]MHz. The measured spurious-free dynamic range (SFDR) was 94[Formula: see text]dB where 17-dB improvement was achieved by applying the randomizers for multi-bit DACs in the first two stages. The peak signal-to-noise and distortion ratio (SNDR) was 76.9[Formula: see text]dB at [Formula: see text]1 dBFS @ 2.5-MHz input, and the figure-of-merit (FOM) was 126[Formula: see text]pJ/conv.

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