A new Doherty amplifier design approach

Author(s):  
Tian He ◽  
Uma Balaji
Frequenz ◽  
2021 ◽  
Vol 0 (0) ◽  
Author(s):  
Saeedeh Lotfi ◽  
Saeed Roshani ◽  
Sobhan Roshani ◽  
Maryam Shirzadian Gilan

Abstract This paper presents a new Doherty power amplifier (DPA) with harmonics suppression. A Wilkinson power divider (WPD) with open-ended and short-ended stubs is designed to suppress unwanted signals. To design the power divider in the circuit of the DPA, even and odd mode analyses are utilized. The proposed design operates at range of 1.2–1.6 GHz. The linearity of the suggested DPA is increased about 6 dBm, in comparison with the main amplifier. The designed Doherty amplifier has a power added efficiency (PAE), drain efficiency (DE) and Gain about 60, 61% and 19 dB, respectively. The designed WPD suppresses 2nd up to 14th harmonics with more than 20 dB suppression level, which is useful for suppressing unwanted harmonics in DPA design. ATF-34143 transistors (pHEMT technology) are used for this DPA amplifier design. The main amplifier has class-F topology and class-F inverse topology is used for auxiliary amplifier.


2012 ◽  
Vol 2012 ◽  
pp. 1-10 ◽  
Author(s):  
Eric Basham ◽  
David Parent

Neurons cultured directly over open-gate field-effect transistors result in a hybrid device, the neuron-FET. Neuron-FET amplifier circuits reported in the literature employ the neuron-FET transducer as a current-mode device in conjunction with a transimpedance amplifier. In this configuration, the transducer does not provide any signal gain, and characterization of the transducer out of the amplification circuit is required. Furthermore, the circuit requires a complex biasing scheme that must be retuned to compensate for drift. Here we present an alternative strategy based on thegm/Iddesign approach to optimize a single-stage common-source amplifier design. Thegm/Iddesign approach facilitates in circuit characterization of the neuron-FET and provides insight into approaches to improving the transistor process design for application as a neuron-FET transducer. Simulation data for a test case demonstrates optimization of the transistor design and significant increase in gain over a current mode implementation.


Author(s):  
Khaled Bathich ◽  
Georg Boeck

This paper presents the analysis and design of a wideband asymmetrical Doherty amplifier. The frequency response of the output combining network of the Doherty amplifier with arbitrary back-off level configuration is analyzed. Other bandwidth-limiting factors were discussed and analyzed as well. A number of performance enhancement techniques were taken into consideration to obtain high and flat back-off efficiency over the amplifier design band of 1.7–2.25 GHz. The designed Doherty amplifier had, at 8.0–9.9 dB output back-off, a minimum efficiency of η = 50% [power-added efficiency of 45%], measured near 40 dBm of output power, and over 28% bandwidth. Using digital predistortion (DPD) linearization, an adjacent-channel leakage ratio (ACLR) of −43 dBc was obtained for a single-carrier W-CDMA signal, at 40.9 dBm and 46% of average output power and drain efficiency, respectively. The designed amplifier represents the first wideband Doherty amplifier reported over extended power back-off range.


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