Advanced Air Gap Process for Multi-Level-Cell Flash Memories Reducing Threshold Voltage Interference and Realizing High Reliability

2007 ◽  
Vol 46 (4B) ◽  
pp. 2184-2187 ◽  
Author(s):  
Keisuke Tsukamoto ◽  
Tatsunori Murata ◽  
Tatsuya Fukumura ◽  
Fumihito Ohta ◽  
Takayuki Yoshitake ◽  
...  
2019 ◽  
Vol 36 ◽  
pp. 100747
Author(s):  
Reza A. Ashrafi ◽  
Suayb S. Arslan ◽  
Ali E. Pusane

2006 ◽  
Author(s):  
K. Tsukamoto ◽  
T. Murata ◽  
T. Fukumura ◽  
F. Ohta ◽  
T. Yoshitake ◽  
...  

MRS Bulletin ◽  
1995 ◽  
Vol 20 (11) ◽  
pp. 53-56 ◽  
Author(s):  
Kuniko Kikuta

The scaling of integrated-circuit device dimensions in the horizontal direction has caused an increase in aspect ratios of contact holes and vias without a corresponding scaledown in vertical dimensions. Conventional sputtering has become unreliable for handling higher aspect-ratio via/contact holes because of its poor step coverage. Several studies have attempted to overcome this problem by using W-CVD and reflow technology. The W-CVD is used for practical device fabrications. However, this technique has several problems such as poor adhesion to SiO2, poor W surface morphology, greater resistivity than Al, and the need of an etch-back process.Al reflow technology using a conventional DC magnetron sputtering system can simplify device-fabrication processes and achieve high reliability without Al/W interfaces. In particular, the Al reflow technology is profitable for multi-level interconnections in combination with a damascene process by using Al chemical mechanical polishing (CMP). These interconnections are necessary for miniaturized and high-speed devices because they provide lower resistivity than W and simplify fabrication processes, resulting in lower cost.This article describes recent Al reflow sputtering technologies as well as application of via and interconnect metallization.


2017 ◽  
Vol 26 (1) ◽  
pp. 018502 ◽  
Author(s):  
Yiming Liao ◽  
Xiaoli Ji ◽  
Yue Xu ◽  
Chengxu Zhang ◽  
Qiang Guo ◽  
...  

Author(s):  
SHAMBHU J. UPADHYAYA ◽  
I-SHYAN HWANG

This paper presents a novel technique for the enhancement of operational reliability of processor arrays by a multi-level fault-tolerant design approach. The key idea of the design is based on the well known hierarchical design paradigm. The proposed fault-tolerant architecture uses a flexible reconfiguration of redundant nodes, thereby offering a better spare utilization than existing two-level redundancy schemes. A variable number of spares is provided at each level of redundancy which enables a flexible reconfiguration as well as area efficient layouts and better spare utilization. The spare nodes at each level can replace any of the failed primary nodes, not only at the same level but also those at the lower levels. The architecture can be adopted to increase the system reliability in Multi Chip Modules (MCMs). The main contributions of our work are the higher degree of fault tolerance, higher overall reliability, flexibility, and a better spare utilization.


2006 ◽  
Vol 83 (11-12) ◽  
pp. 2150-2154 ◽  
Author(s):  
R.J.O.M. Hoofman ◽  
R. Caluwaerts ◽  
J. Michelon ◽  
P. Herrero Bernabé ◽  
J.P. Gueneau de Mussy ◽  
...  
Keyword(s):  
Air Gap ◽  

2019 ◽  
Vol 963 ◽  
pp. 749-752
Author(s):  
Jose Ortiz Gonzalez ◽  
Olayiwola Alatise ◽  
Philip A. Mawby

The material properties of SiC make SiC power devices a superior alternative to the conventional Si power devices. However, the reliability of the gate oxide has been a major concern, limiting the adoption of SiC power MOSFETs as the power semiconductor of choice in applications which demand a high reliability. The threshold voltage (VTH) shift caused by Bias Temperature Instability (BTI) has focused the attention of different researchers, with multiple publications on this topic. This paper presents a novel method for evaluating the threshold voltage shift due to negative gate bias and its recovery when the gate bias stress is removed. This method could enable gate oxide reliability assessment techniques and contribute to new qualification methods.


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