Evaluation Of The MARS Fault Tolerance Mechanisms Using Three Physical Fault Injection Techniques

2005 ◽  
Author(s):  
J. Karlsson ◽  
P. Folkesson ◽  
J. Arlat ◽  
Y. Crouzet ◽  
G. Leber ◽  
...  
Keyword(s):  
Fault Tolerance ◽  
Fault Injection ◽  
Tolerance Mechanisms ◽  
Injection Techniques

scholarly journals ARINC653 Channel Robustness Verification Using LeonViP-MC, a LEON4 Multicore Virtual Platform

Electronics ◽  
2021 ◽  
Vol 10 (10) ◽  
pp. 1179
Author(s):  
Jonatan Sánchez ◽  
Antonio da Silva ◽  
Pablo Parra ◽  
Óscar R. Polo ◽  
Agustín Martínez Hellín ◽  
...  
Keyword(s):  
Fault Tolerance ◽  
Architectural Design ◽  
Fault Injection ◽  
Control Unit ◽  
Tolerance Mechanisms ◽  
Efficient Data ◽  
Instrument Control ◽  
Virtual Platform ◽  
Hardware Platforms ◽  
The University

Multicore hardware platforms are being incorporated into spacecraft on-board systems to achieve faster and more efficient data processing. However, such systems lead to increased complexity in software development and represent a considerable challenge, especially concerning the runtime verification of fault-tolerance requirements. To address the ever-challenging verification of this kind of requirement, we introduce a LEON4 multicore virtual platform called LeonViP-MC. LeonViP-MC is an evolution of a previous development called Leon2ViP, carried out by the Space Research Group of the University of Alcalá (SRG-UAH), which has been successfully used in the development and testing of the flight software of the instrument control unit (ICU) of the energetic particle detector (EPD) on board the Solar Orbiter. This paper describes the LeonViP-MC architectural design decisions oriented towards fault-injection campaigns to verify software fault-tolerance mechanisms. To validate the simulator, we developed an ARINC653 communications channel that incorporates fault-tolerance mechanisms and is currently being used to develop a hypervisor level for the GR740 platform.

scholarly journals Synthesis of Classical and Non-Classical CMOS Transistor Fault Models Mapped to Gate-Level for Reconfigurable Hardware-Based Fault Injection

2021 ◽  
Author(s):  
Raha Abedi
Keyword(s):  
Fault Tolerance ◽  
Fault Injection ◽  
Cost Effective ◽  
Fault Model ◽  
Reconfigurable Hardware ◽  
Fault Models ◽  
System Complexity ◽  
Synthesis Time ◽  
Cmos Transistor ◽  
Injection Techniques

One of the main goals of fault injection techniques is to evaluate the fault tolerance of a design. To have greater confidence in the fault tolerance of a system, an accurate fault model is essential. While more accurate than gate level, transistor level fault models cannot be synthesized into FPGA chips. Thus, transistor level faults must be mapped to the gate level to obtain both accuracy and synthesizability. Re-synthesizing a large system for fault injection is not cost effective when the number of faults and system complexity are high. Therefore, the system must be divided into partitions to reduce the re-synthesis time as faults are injected only into a portion of the system. However, the module-based partial reconfiguration complexity rises with an increase in the total number of partitions in the system. An unbalanced partitioning methodology is introduced to reduce the total number of partitions in a system while the size of the partitions where faults are to be injected remains small enough to achieve an acceptable re-synthesis time.

scholarly journals Synthesis of Classical and Non-Classical CMOS Transistor Fault Models Mapped to Gate-Level for Reconfigurable Hardware-Based Fault Injection

2021 ◽  
Author(s):  
Raha Abedi
Keyword(s):  
Fault Tolerance ◽  
Fault Injection ◽  
Cost Effective ◽  
Fault Model ◽  
Reconfigurable Hardware ◽  
Fault Models ◽  
System Complexity ◽  
Synthesis Time ◽  
Cmos Transistor ◽  
Injection Techniques

One of the main goals of fault injection techniques is to evaluate the fault tolerance of a design. To have greater confidence in the fault tolerance of a system, an accurate fault model is essential. While more accurate than gate level, transistor level fault models cannot be synthesized into FPGA chips. Thus, transistor level faults must be mapped to the gate level to obtain both accuracy and synthesizability. Re-synthesizing a large system for fault injection is not cost effective when the number of faults and system complexity are high. Therefore, the system must be divided into partitions to reduce the re-synthesis time as faults are injected only into a portion of the system. However, the module-based partial reconfiguration complexity rises with an increase in the total number of partitions in the system. An unbalanced partitioning methodology is introduced to reduce the total number of partitions in a system while the size of the partitions where faults are to be injected remains small enough to achieve an acceptable re-synthesis time.

FPGA-Based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits

2001 ◽  
pp. 493-502 ◽  
Author(s):  
Pierluigi Civera ◽  
Luca Macchiarulo ◽  
Maurizio Rebaudengo ◽  
Matteo Sonza Reorda ◽  
Massimo Violante
Keyword(s):  
Fault Tolerance ◽  
Fault Injection ◽  
Vlsi Circuits ◽  
Fast Evaluation ◽  
Injection Techniques

scholarly journals Towards On-line Adaptation of Fault Tolerance Mechanisms

2010 ◽  
Author(s):  
Jean-Charles Fabre ◽  
Marc-Olivier Killijian ◽  
Thomas Pareaud
Keyword(s):  
Fault Tolerance ◽  
Tolerance Mechanisms ◽  
On Line

A Design for Fault-Tolerant Communication Middleware Based on Time-Triggered

2014 ◽  
Vol 548-549 ◽  
pp. 1326-1329
Author(s):  
Juan Jin ◽  
Qing Fan Gu
Keyword(s):  
Fault Tolerance ◽  
Real Time ◽  
Fault Location ◽  
Fault Tolerant ◽  
Application Software ◽  
Tolerance Mechanisms ◽  
The Real ◽  
Communication Middleware ◽  
Fault Mechanism ◽  
Health Diagnosis

Against to the unsustainable problems of health diagnosis, fault location and fault tolerance mechanisms that existing in the current avionics applications, we proposed a fault-tolerant communication middleware which is based on time-triggered in this paper. This middleware is designed to provide a support platform for applications of the real-time based on communication middleware. From the communication middleware level and also combined with time-triggered mechanism and fault-tolerant strategy, it diagnoses the general faults first, and then routes them to the appropriate fault mechanism to process it. So the middleware completely separates fault-tolerant process from the application software functions.

A Method to Support Fault Tolerance Design in Service Oriented Computing Systems

2012 ◽  
pp. 362-376
Author(s):  
Domenico Cotroneo ◽  
Antonio Pecchia ◽  
Roberto Pietrantuono ◽  
Stefano Russo
Keyword(s):  
Fault Tolerance ◽  
Common Ground ◽  
Fault Injection ◽  
Failure Behavior ◽  
Tolerance Design ◽  
System Failure ◽  
Computing Systems ◽  
Service Oriented Computing ◽  
Service Oriented ◽  
Tailored Design

Service Oriented Computing relies on the integration of heterogeneous software technologies and infrastructures that provide developers with a common ground for composing services and producing applications flexibly. However, this approach eases software development but makes dependability a big challenge. Integrating such diverse software items raise issues that traditional testing is not able to exhaustively cope with. In this context, tolerating faults, rather than attempt to detect them solely by testing, is a more suitable solution. This paper proposes a method to support a tailored design of fault tolerance actions for the system being developed. This paper describes system failure behavior through an extensive fault injection campaign to figure out its criticalities and adopt the most appropriate countermeasures to tolerate operational faults. The proposed method is applied to two distinct SOC-enabling technologies. Results show how the achieved findings allow designers to understand the system failure behavior and plan fault tolerance.

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