Efficient Identification of Promising Regions in High-Dimensional Design Spaces With Multilevel Materials Design Applications

2018 ◽  
Author(s):  
Clinton Morris ◽  
Carolyn C. Seepersad
Keyword(s):  
Spectral Clustering ◽  
High Performance ◽  
Design Space Exploration ◽  
Design Space ◽  
Space Structure ◽  
Three Dimensions ◽  
High Dimensional ◽  
Underlying Structure ◽  
Large Sets ◽  
Multiple Regions

Design space exploration can reveal the underlying structure of design problems of interest. In a set-based approach, for example, exploration can identify sets of designs or regions of the design space that meet specific performance requirements. For some problems, promising designs may cluster in multiple regions of the design space, and the boundaries of those clusters may be irregularly shaped and difficult to predict. Visualizing the promising regions can clarify the design space structure, but design spaces are typically high-dimensional, making it difficult to visualize the space in three dimensions. Techniques have been introduced to map high-dimensional design spaces to low-dimensional, visualizable spaces. Before the promising regions can be visualized, however, the first task is to identify how many clusters of promising designs exist in the high-dimensional design space. Unsupervised machine learning methods, such as spectral clustering, have been utilized for this task. Spectral clustering is generally accurate but becomes computationally intractable with large sets of candidate designs. Therefore, in this paper a technique for accurately identifying clusters of promising designs is introduced that remains viable with large sets of designs. The technique is based on spectral clustering but reduces its computational impact by leveraging the Nyström Method in the formulation of self-tuning spectral clustering. After validating the method on a simplified example, it is applied to identify clusters of high performance designs for a high-dimensional negative stiffness metamaterials design problem.

Visualizing and Evaluating High-Dimensional Mappings of Sets of High Performance Designs

2019 ◽  
Author(s):  
Clinton B. Morris ◽  
Michael R. Haberman ◽  
Carolyn C. Seepersad
Keyword(s):  
High Performance ◽  
Design Space Exploration ◽  
Design Space ◽  
Space Structure ◽  
Three Dimensions ◽  
High Dimensional ◽  
Underlying Structure ◽  
Visualization Technique ◽  
Two Stage ◽  
Input Design

Abstract Design space exploration can reveal the underlying structure of design problems. In a set-based approach, for example, exploration can map sets of designs or regions of the design space that meet specific performance requirements. For some problems, promising designs may cluster in multiple regions of the input design space, and the boundaries of those clusters may be irregularly shaped and difficult to predict. Visualizing the promising regions can clarify the design space structure, but design spaces are typically high-dimensional, making it difficult to visualize the space in three dimensions. To convey the structure of such high-dimensional design regions, a two-stage approach is proposed to (1) identify and (2) visualize each distinct cluster or region of interest in the input design space. This paper focuses on the visualization stage of the approach. Rather than select a singular technique to map high-dimensional design spaces to low-dimensional, visualizable spaces, a selection procedure is investigated. Metrics are available for comparing different visualizations, but the current metrics either overestimate the quality or favor selection of certain visualizations. Therefore, this work introduces and validates a more objective metric, termed preservation, to compare the quality of alternative visualization strategies. Furthermore, a new visualization technique previously unexplored in the design automation community, t-Distributed Neighbor Embedding, is introduced and compared to other visualization strategies. Finally, the new metric and visualization technique are integrated into a two-stage visualization strategy to identify and visualize clusters of high-performance designs for a high-dimensional negative stiffness metamaterials design problem.

Identification of High Performance Regions of High-Dimensional Design Spaces With Materials Design Applications

2017 ◽  
Author(s):  
Clinton Morris ◽  
Carolyn C. Seepersad
Keyword(s):  
Spectral Clustering ◽  
High Performance ◽  
Design Space ◽  
Dimensional Space ◽  
Pareto Frontier ◽  
Materials Design ◽  
Underlying Structure ◽  
Pareto Solutions ◽  
Visualization Tools ◽  
Future Work

Design exploration methods seek to identify sets of candidate designs or regions of the design space that yield desirable performance. Commonly, the dimensionality of the design space exceeds the limited dimensions supported by standard graphical techniques, making it difficult for human designers to visualize or understand the underlying structure of the design space. With standard visualization tools, it is sometimes challenging to visualize a multi-dimensional Pareto frontier, but it is even more difficult to visualize the collections of design (input) variable values that yield those Pareto solutions. It is difficult for a designer to determine not only how many distinct regions of the design (input) space may offer desirable performance but also how those design spaces are structured. In this paper, a form of spectral clustering known as ε-neighborhood clustering is proposed for identifying satisfactory regions in the design spaces of multilevel problems. By exploiting properties of graph theory, the number of satisfactory design regions can be determined accurately and efficiently, and the design space can be partitioned. The method is demonstrated to be effective at identifying clusters in a 10 dimensional space. It is also applied to a multilevel materials design problem to demonstrate its efficacy on a realistic design application. Future work intends to visualize each individually identified design region to produce an intuitive mapping of the design space.

scholarly journals Evaluation of Static Mapping for Dynamic Space-Shared Multi-task Processing on FPGAs

2021 ◽  
Author(s):  
Umar Ibrahim Minhas ◽  
Roger Woods ◽  
Georgios Karakonstantis
Keyword(s):  
High Performance ◽  
Design Space Exploration ◽  
Design Space ◽  
System Throughput ◽  
Design Parameters ◽  
Temporal Constraints ◽  
Shared Resources ◽  
Task Processing ◽  
High Level ◽  
Performance Computing

AbstractWhilst FPGAs have been used in cloud ecosystems, it is still extremely challenging to achieve high compute density when mapping heterogeneous multi-tasks on shared resources at runtime. This work addresses this by treating the FPGA resource as a service and employing multi-task processing at the high level, design space exploration and static off-line partitioning in order to allow more efficient mapping of heterogeneous tasks onto the FPGA. In addition, a new, comprehensive runtime functional simulator is used to evaluate the effect of various spatial and temporal constraints on both the existing and new approaches when varying system design parameters. A comprehensive suite of real high performance computing tasks was implemented on a Nallatech 385 FPGA card and show that our approach can provide on average 2.9 × and 2.3 × higher system throughput for compute and mixed intensity tasks, while 0.2 × lower for memory intensive tasks due to external memory access latency and bandwidth limitations. The work has been extended by introducing a novel scheduling scheme to enhance temporal utilization of resources when using the proposed approach. Additional results for large queues of mixed intensity tasks (compute and memory) show that the proposed partitioning and scheduling approach can provide higher than 3 × system speedup over previous schemes.

scholarly journals Core-Level Modeling and Frequency Prediction for DSP Applications on FPGAs

2015 ◽  
Vol 2015 ◽  
pp. 1-20
Author(s):  
Gongyu Wang ◽  
Greg Stitt ◽  
Herman Lam ◽  
Alan George
Keyword(s):  
High Performance ◽  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration ◽  
Core Level ◽  
Prediction Methods ◽  
Clock Frequency ◽  
Worst Case ◽  
Model Based ◽  
Dsp Applications

Field-programmable gate arrays (FPGAs) provide a promising technology that can improve performance of many high-performance computing and embedded applications. However, unlike software design tools, the relatively immature state of FPGA tools significantly limits productivity and consequently prevents widespread adoption of the technology. For example, the lengthy design-translate-execute (DTE) process often must be iterated to meet the application requirements. Previous works have enabled model-based, design-space exploration to reduce DTE iterations but are limited by a lack of accurate model-based prediction of key design parameters, the most important of which is clock frequency. In this paper, we present a core-level modeling and design (CMD) methodology that enables modeling of FPGA applications at an abstract level and yet produces accurate predictions of parameters such as clock frequency, resource utilization (i.e., area), and latency. We evaluate CMD’s prediction methods using several high-performance DSP applications on various families of FPGAs and show an average clock-frequency prediction error of 3.6%, with a worst-case error of 20.4%, compared to the best of existing high-level prediction methods, 13.9% average error with 48.2% worst-case error. We also demonstrate how such prediction enables accurate design-space exploration without coding in a hardware-description language (HDL), significantly reducing the total design time.

A Fast Design Space Exploration Method for Reconfigurable Architecture Based on Loop Optimization

2011 ◽  
Vol 467-469 ◽  
pp. 812-817 ◽  
Author(s):  
Dan Zhang ◽  
Rong Cai Zhao ◽  
Lin Han ◽  
Wei Fang Liang ◽  
Jin Qu ◽  
...  
Keyword(s):  
High Performance ◽  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration ◽  
General Purpose ◽  
Parallel Execution ◽  
Data Reuse ◽  
Loop Optimization ◽  
Fpga Chip ◽  
The Times

Using FPGA for general-purpose computation has become a hot research topic in high-performance computing technologies. However, the complexity of design and resource of FPGA make applying a common approach to solve the problem with mixed constraints impossible. Aiming at familiar loop structure of the applications, a design space exploration method based on FPGA hardware constrains is proposed according to the FPGA chip features, which combines the features of the corresponding application to perform loop optimization for reducing the demand of memory. Experimental results show that the method significantly improves the rate of data reuse, reduces the times of external memory access, achieves parallel execution of multiple pipelining, and effectively improves the performance of applications implemented on FPGA.

scholarly journals Design space exploration in near-data co-processors for general-purpose acceleration, in high-performance and low-power processing environments

2021 ◽  
Author(s):  
Αθανάσιος Τζιουβάρας
Keyword(s):  
Low Power ◽  
High Performance ◽  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration ◽  
General Purpose

Οι σύγχρονες αρχιτεκτονικές υπολογιστών είναι αντιμέτωπες με ένα σοβαρό πρόβλημα που αφορά την κλιμάκωση της απόδοσης τους, καθώς η συμφόρηση της πληροφορίας έχει μετατοπιστεί από τον πυρήνα του επεξεργαστή στην μονάδα της κύριας μνήμης και στις λειτουργίες μεταφοράς δεδομένων. Το φαινόμενο αυτό μπορεί μερικώς να αποδοθεί στο τέλος της ισχύος του νόμου του Dennard και στην διαρκή μείωση του μεγέθους των τρανσίστορς. Ως αποτέλεσμα, η πυκνότητα ισχύος των ολοκληρωμένων κυκλωμάτων έχει αυξηθεί τόσο, ώστε η λειτουργία των πολύ-πυρηνικών επεξεργαστών να επιτελείται σε τάσεις που βρίσκονται κοντά στην τάση κατωφλίου. Για να ξεπεράσουν το πρόβλημα αυτό, οι ερευνητές τείνουν να αποκλίνουν από τις κλασικές αρχιτεκτονικές προσεγγίσεις τύπου Von Neuman και να στρέφουν την προσοχή τους σε νέα μοντέλα επεξεργασίας. Την τελευταία δεκαετία έχει παρατηρηθεί μία αναζωπύρωση του ενδιαφέροντος για το παράδειγμα εκτέλεσης εντολών κοντά στην κύρια μνήμη (NDP), κατά το οποίο οι εντολές εκτελούνται στο κύκλωμα της κύριας μνήμης αντί του κεντρικού επεξεργαστή. Έτσι, ο αριθμός των λειτουργιών της μεταφοράς δεδομένων μεταξύ της κύριας μνήμης και του επεξεργαστή μειώνεται σημαντικά, κάτι το οποίο επιδρά θετικά στην κατανάλωση ισχύος και την επιτεύξιμη απόδοση του συστήματος. Κινούμενοι προς αυτήν την υπόθεση, στην διατριβή αυτή εξερευνούμε το NDP παράδειγμα για επεξεργαστές υψηλής απόδοσης αλλά και για επεξεργαστές χαμηλούς ισχύος. Όσον αφορά του επεξεργαστές υψηλής απόδοσης, προτείνουμε μία προσέγγιση στην οποία λαμβάνουμε υπ’ όψη μας την εκτέλεση βρόγχων γενικού σκοπού. H αρχιτεκτονική την οποία προτείνουμε κάνει χρήση μίας μεθοδολογίας χρονοδρομολόγησης εντολών, κατά την οποία η κάθε εντολή του βρόγχου εκδίδεται σε ένα ειδικά προσαρμοσμένο ολοκληρωμένο κύκλωμα που έχει τον ρόλο του επιταχυντή της εκτέλεσης του βρόγχου. Το κύκλωμα αυτό τοποθετείται στο λογικό επίπεδο μίας κύριας μνήμης υβριδικού κύβου (HMC). Στο επίπεδο αυτό οι εντολές εκτελούνται επαναληπτικά και παράλληλα, με έναν τρόπο που θυμίζει αυτόν της επικάλυψης λογισμικού, ενώ τα ενδιάμεσα παραγόμενα αποτελέσματα παροχετεύονται δια μέσου ενός δικτύου διασύνδεσης που βρίσκεται πάνω στο ολοκληρωμένο κύκλωμα. Όσον αφορά τις αρχιτεκτονικές χαμηλής κατανάλωσης ισχύος, αναπτύσσουμε μία καινοτόμο μεθοδολογία ανάλυσης χρονισμού, η οποία βασίζεται στις αρχές του STA και προσανατολίζεται συγκεκριμένα προς συστήματα χαμηλών προδιαγραφών και χαμηλής κατανάλωσης ενέργειας. Η μεθοδολογία αυτή λαμβάνει υπ’ όψη της την διέγερση των διαδρομών χρονισμού της κάθε εντολής που υποστηρίζεται από το σετ εντολών του επεξεργαστή (ISA) και υπολογίζει την καθυστέρηση της χειρότερης περίπτωσης για την κάθε εντολή ξεχωριστά. Ως αποτέλεσμα, αντλούμε πληροφορίες για την χρονική καθυστέρηση σε επίπεδο εντολής και εκμεταλλευόμαστε την πληροφορία αυτή ώστε να κλιμακώνουμε την συχνότητα του ρολογιού δυναμικά, ανάλογα με τον τύπο εντολής που εκτελείται στο κύκλωμα σε κάθε χρονική στιγμή. Στην συνέχεια χρησιμοποιούμε την μεθοδολογία που περιγράψαμε για να συν-σχεδιάσουμε μία αρχιτεκτονική, με γνώμονα την δυναμική μεταβολή της συχνότητας του ρολογιού του επεξεργαστή η οποία εκτείνεται στον βαθμό λεπτομέρειας του κύκλου μηχανής. Επικεντρωνόμαστε ξανά στην εκτέλεση κώδικα γενικού σκοπού και υλοποιούμε συνδυαστικά τη αρχιτεκτονική στο λογικό επίπεδο μίας μνήμης τύπου HMC ώστε να καταστήσουμε ικανό το σύστημα μας για εκτέλεση εντολών δίπλα στην μνήμη τυχαίας προσπέλασης. Επιλέγουμε να αξιολογήσουμε τις αρχιτεκτονικές που υλοποιήσαμε (της υψηλής απόδοσης αλλά και της χαμηλής κατανάλωσης ισχύος) σε επίπεδο υλοποίησης ολοκληρωμένου κυκλώματος σύμφωνα με τα πρότυπα της βιομηχανίας ώστε να ενισχύσουμε την εγκυρότητας της μεθοδολογίας μας. Τα αποτελέσματα τα οποία παίρνουμε υποδεικνύουνε μία μεγάλη αύξηση της απόδοσης του συστήματος όσον αφορά την επιτάχυνση της λειτουργίας του σε σύγκριση με την αρχική αρχιτεκτονική, ενώ η κατανάλωση ισχύος πέφτει σε πολύ χαμηλά επίπεδα.

Design Space Exploration in Sparse, Mixed Continuous/Discrete Spaces via Synthetically Enhanced Classification

2018 ◽  
Author(s):  
Tyler Wiest ◽  
Carolyn Conner Seepersad ◽  
Michael Haberman
Keyword(s):  
High Performance ◽  
Design Space Exploration ◽  
Design Space ◽  
Regions Of Interest ◽  
High Performing ◽  
Bayesian Network Classifiers ◽  
Design Variables ◽  
Complex Engineering ◽  
Low Performance ◽  
Discrete Spaces

Exploration of a design space is the first step in identifying sets of high-performing solutions to complex engineering problems. For this purpose, Bayesian network classifiers (BNCs) have been shown to be effective for mapping regions of interest in the design space, even when those regions of interest exhibit complex topologies. However, identifying sets of desirable solutions can be difficult with a BNC when attempting to map a space where high-performance designs are spread sparsely among a disproportionately large number of low-performance designs, resulting in an imbalanced classifier. In this paper, a method is presented that utilizes probabilities of class membership for known training points, combined with interpolation between those points, to generate synthetic high-performance points in a design space. By adding synthetic design points into the BNC training set, a designer can rebalance an imbalanced classifier and improve classification accuracy throughout the space. For demonstration, this approach is applied to an acoustics metamaterial design problem with a sparse design space characterized by a combination of discrete and continuous design variables.

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