High Digital Speed Level-2 Interconnections via a New Microcontact Design

2001 ◽  
Author(s):  
Dariusz R. Pryputniewicz ◽  
Dimitry G. Grabbe ◽  
Ryszard J. Pryputniewicz
Keyword(s):  
Process Optimization ◽  
Electronic Packaging ◽  
High Density ◽  
Density Level ◽  
Speed Level ◽  
Material Utilization ◽  
Level 2

Abstract Requirements for high digital speed, high density, level-2 interconnections have led to development of a new microcontact. Design of this microcontact allows for separable and reusable interconnections. In this paper, we discuss methodology used to develop the microcontact, allowing 100% material utilization, present its design, including analysis and process optimization, and summarize its characteristics as they relate to electronic packaging.

Lithography Process Challenges for 3D and 2.5D Applications

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 000398-000424
Author(s):  
Doug Shelton ◽  
Tomii Kume
Keyword(s):  
High Resolution ◽  
Process Optimization ◽  
Mass Production ◽  
Low Cost ◽  
High Density ◽  
Through Silicon Via ◽  
Key Technology ◽  
Lithography Process ◽  
Advanced Packaging

Lithography process optimization is a key technology enabling mass production of high-density interconnects using 3D and 2.5D technologies. In this paper, Canon will continue its discussion of lithography optimization of thick-resist profiles and overlay accuracy to increase process margins for Through-Silicon Via (TSV) and Redistribution Layer (RDL) applications. Canon will also provide updates on the FPA-5510iV and FPA-5510iZ i-line steppers that are gaining acceptance as high-resolution, and low-cost lithography solutions for aggressive advanced packaging, 3D and 2.5D applications.

Z-Interconnect Technology - A Reliable, Cost Efficient Solution for High Density, High Performance Electronic Packaging

2014 ◽  
Vol 2014 (1) ◽  
pp. 000141-000147 ◽  
Author(s):  
John M. Lauffer ◽  
Kevin Knadle
Keyword(s):  
Electronic Packaging ◽  
High Performance ◽  
Performance Enhancement ◽  
High Density ◽  
Consumer Electronics ◽  
Electrical Performance ◽  
Printed Wiring Board ◽  
Electrically Conductive Adhesive ◽  
Plated Through Hole ◽  
Interconnect Technology

Common themes across all segments of electronic packaging today are density and performance. High density interconnect (HDI) technology is one of the most commonly utilized methods for electronic package density improvement, while many different areas have been investigated for performance improvement, from low loss dielectric and conductor materials, to via design and via stub reduction. Electrical performance and density requirements are sometimes complementary, but often times, conflicting with one another. This paper will describe the design, materials, fabrication, and reliability of a new Z-Interconnect technology that addresses both high density and high performance demands simultaneously. Z-Interconnect technology uses an electrically conductive adhesive to electrically interconnect several cores (Full Z) or sub-composites (Sub Z) in a single lamination process. Z-Interconnect technology will be compared and contrasted to other commonly used solutions to the performance and density challenges. HDI or sequential build-up technology is a pervasive solution to the density demands in semiconductor packaging and consumer electronics (e.g. Smart phones), but has not caught hold in HPC or A&D printed wiring board (PWB) applications. One solution for PWB electrical performance enhancement is plated through hole (PTH) stub reduction by “back drilling” the unwanted portion of the PTH. Pb-free reflow and Current Induced Thermal Cycling (CITC) test results of product coupons and specially designed test vehicles, having component pitches down to 0.4mm, will be presented. Z-Interconnect test vehicles have survived 6X Pb-free (260C) reflow cycles, followed by greater than 3000 cycles of 23C–150C CITC cycles. Test vehicle and product coupons also easily survive 10 or more 23C–260C CITC cycles.

Lithography Process Optimization for 3D and 2.5D Applications

2013 ◽  
Vol 2013 (1) ◽  
pp. 000790-000793 ◽  
Author(s):  
Doug Shelton ◽  
Tomii Kume
Keyword(s):  
High Resolution ◽  
Process Optimization ◽  
Preliminary Data ◽  
Mass Production ◽  
Low Cost ◽  
High Density ◽  
Through Silicon Via ◽  
Key Technology ◽  
Lithography Process ◽  
Advanced Packaging

Lithography process optimization is a key technology enabling mass production of high-density interconnects using 3D and 2.5D technologies. In this paper, Canon continues its investigation of lithography optimization of thick-resist profiles and overlay accuracy to increase process margins for Through-Silicon Via (TSV) and Redistribution Layer (RDL) applications. Canon will also provide updates on the FPA-5510iV and FPA-5510iZ i-line steppers that are gaining acceptance as high-resolution, and low-cost lithography solutions for aggressive advanced packaging, 3D and 2.5D applications also preliminary data illustrating 450 mm wafer process challenges.

Advanced Process Technology for 3D and 2.5D Applications

2014 ◽  
Vol 2014 (1) ◽  
pp. 000905-000911
Author(s):  
Doug Shelton ◽  
Tomii Kume ◽  
Charles Wang ◽  
Alex Hubbard ◽  
Cody Murray ◽  
...  
Keyword(s):  
Process Optimization ◽  
Mass Production ◽  
High Density ◽  
Process Technology ◽  
Profile Control ◽  
Additional Product

Advanced process technology is required to develop and enable mass production of high-density 3D and 2.5D interconnect technologies. In this paper, Canon and IBM @ Albany NanoTech will present process optimization results for lithography applications requiring precise thick-resist profile control and precise overlay accuracy of distorted patterns on bonded process wafers. Canon will also provide additional product updates from Canon Anelva.

Growth of SiC Microwires through Si Microwires Carburization

2011 ◽  
Vol 679-680 ◽  
pp. 512-515 ◽  
Author(s):  
Maelig Ollivier ◽  
Arnaud Mantoux ◽  
Edwige Bano ◽  
Konstantinos Rogdakis ◽  
Konstantinos Zekentes ◽  
...  
Keyword(s):  
Surface Roughness ◽  
Raman Spectroscopy ◽  
Process Optimization ◽  
Gold Catalyst ◽  
Stacking Faults ◽  
Morphological Characterization ◽  
High Density ◽  
Silicon Microwires

Silicon microwires (MWs) previously synthesized using the VLS method with gold catalyst are being carburized at 1100°C under methane aiming to their conversion to SiC. SEM, TEM as well as XPS and Raman spectroscopy were used for structural and morphological characterization. After carburization achievement, SiC is found to be polycrystalline with a high density of stacking faults associated to an increase of surface roughness. Directions for the carburization process optimization are given.

scholarly journals Implementing the ISO 15746 Standard for Chemical Process Optimization

2016 ◽  
Author(s):  
Guodong Shao ◽  
Peter Denno ◽  
Albert Jones ◽  
Yan Lu
Keyword(s):  
Process Control ◽  
Process Optimization ◽  
Data Model ◽  
Numerical Optimization ◽  
Chemical Process ◽  
Optimization Problem ◽  
Modeling Tools ◽  
Advanced Process Control ◽  
Chemical Process Optimization ◽  
Level 2

This paper proposes an approach to integrating advanced process control solutions with optimization (APC-O) solutions, within any factory, to enable more efficient production processes. Currently, vendors who provide the software applications that implement control solutions are isolated and relatively independent. Each such solution is designed to implement a specific task such as control, simulation, and optimization — and only that task. It is not uncommon for vendors to use different mathematical formalisms and modeling tools that produce different data representations and formats. Moreover, instead of being modeled uniformly only once, the same knowledge is often modeled multiple times — each time using a different, specialized abstraction. As a result, it is extremely difficult to integrate optimization with advanced process control. We believe that a recent standard, International Organization for Standardization (ISO) 15746, describes a data model that can facilitate that integration. In this paper, we demonstrate a novel method of integrating advanced process control using ISO 15746 with numerical optimization. The demonstration is based on a chemical-process-optimization problem, which resides at level 2 of the International Society of Automation (ISA) 95 architecture. The inputs to that optimization problem, which are captured in the ISO 15746 data model, come in two forms: goals from level 3 and feedback from level 1. We map these inputs, using this data model, to a population of a meta-model of the optimization problem for a chemical process. Serialization of the metamodel population provides input to a numerical optimization code of the optimization problem. The results of this integrated process, which is automated, provide the solution to the originally selected, level 2 optimization problem.

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