Prognostic Health Monitoring Method for Fatigue Failure of Solder Joints on Printed Circuit Boards Based on a Canary Circuit

Author(s):  
Kenji Hirohata ◽  
Yousuke Hisakuni ◽  
Takahiro Omori ◽  
Tomoko Monda ◽  
Minoru Mukai

Continuing improvements in both capacity and miniaturization of electronic equipment such as solid state drives (SSDs) are spurring demand for high-density packaging of NAND-type flash memory mounted on SSD printed circuit boards. High-density packaging leads to increased fatigue failure risk of solder joints due to the decreased reliability margin for stress. We have developed a failure precursor detection technology based on fatigue failure probability estimation during use. This method estimates the cycles to fatigue failure of an actual circuit by detecting broken connections in a canary circuit (a dummy circuit of daisy-chained solder joints). The canary circuit is designed to fail earlier than the actual circuit under the same failure mode by using accelerated reliability testing and inelastic stress simulation. The statistical distribution of the strain range of solder joints can be provided by Monte Carlo simulations based on the finite element method and random load modeling. A feasibility study of the failure probability estimation method is conducted by applying the method to a printed circuit board on which a ball grid array (BGA) package is mounted using BGA solder joints. The proposed method is found to be useful for prognostic health monitoring of solder joint’s fatigue failure.

Author(s):  
Kenji Hirohata ◽  
Yousuke Hisakuni ◽  
Takahiro Omori

Devices mounted on printed circuit boards (PCBs) are subject to temperature variations resulting from power switching and ambient temperature changes, and may be subject to random dynamic load histories from sources such as vibration. Since solder material is mechanically the most ductile part, fatigue failure may occur in solder joints. Health monitoring for fatigue life under field conditions is a key issue for improving availability and serviceability for maintenance. We have developed a failure precursor detection technology and a fatigue life estimation method for ball grid array (BGA) solder joints, based on a canary circuit. This method estimates fatigue failure life of an actual circuit by detecting failure connections in a canary circuit (a dummy circuit of daisy-chained solder joints). The canary circuit is designed to fail before the actual circuit under the same failure mode by using accelerated reliability testing and inelastic stress simulation. A feasibility study of the failure probability estimation method is conducted by applying the method to a PCB on which a BGA component is mounted. It is confirmed that the fatigue life under a thermal cyclic load can be estimated from a canary circuit, that estimation of fatigue life under a random dynamic load is feasible, and that the estimation results are consistent with results from actual random vibration tests. The proposed method is found to be useful for prognostic health monitoring of solder joint fatigue failure.


2011 ◽  
Vol 19 (9) ◽  
pp. 2154-2162 ◽  
Author(s):  
谢宏威 XIE Hong-wei ◽  
张宪民 ZHANG Xian-min ◽  
邝泳聪 KUANG Yong-cong ◽  
欧阳高飞 OUYANG Gao-fei

2020 ◽  
Vol 17 (3) ◽  
pp. 79-88
Author(s):  
Maarten Cauwe ◽  
Bart Vandevelde ◽  
Chinmay Nawghane ◽  
Marnix Van De Slyeke ◽  
Erwin Bosman ◽  
...  

Abstract High-density interconnect (HDI) printed circuit boards (PCBs) and associated assemblies are essential to allow space projects to benefit from the ever increasing complexity and functionality of modern integrated circuits such as field-programmable gate arrays, digital signal processors and application processors. Increasing demands for functionality translate into higher signal speeds combined with an increasing number of input/outputs (I/Os). To limit the overall package size, the contact pad pitch of the components is reduced. The combination of a high number of I/Os with a reduced pitch places additional demands onto the PCB, requiring the use of laser-drilled microvias, high-aspect ratio core vias, and small track width and spacing. Although the associated advanced manufacturing processes have been widely used in commercial, automotive, medical, and military applications, reconciling these advancements in capability with the reliability requirements for space remains a challenge. Two categories of the HDI technology are considered: two levels of staggered microvias (basic HDI) and (up to) three levels of stacked microvias (complex HDI). In this article, the qualification of the basic HDI technology in accordance with ECSS-Q-ST-70-60C is described. At 1.0-mm pitch, the technology passes all testing successfully. At .8-mm pitch, failures are encountered during interconnection stress testing and conductive anodic filament testing. These failures provide the basis for updating the design rules for HDI PCBs.


Sign in / Sign up

Export Citation Format

Share Document