Through-silicon via (TSV) technology is expected to overcome the limitations of I/O density and helps in enhancing system performance of conventional flip chip packages. One of the challenges for producing reliable TSV packages is the stacking and joining of thin wafers or dies. In the case of the conventional solder interconnections, many reliability issues arise at the interface between solder and copper bump. As an alternative solution, Cu-Cu direct thermo-compression bonding (CuDB) is a possible option to enable three-dimension (3D) package integration. CuDB has several advantages over the solder based micro bump joining, such as reduction in soldering process steps, enabling higher interconnect density, enhanced thermal conductivity and decreased concerns about intermetallic compounds (IMC) formation. Critical issue of CuDB is bonding interface condition. After the bonding process, Cu-Cu direct bonding interface is obtained. However, several researchers have reported small voids at the bonded interface. These defects can act as an initial crack which may lead to eventual fracture of the interface. The fracture could happen due to the thermal expansion coefficient (CTE) mismatch between the substrate and the chip during the postbonding process, board level reflow or thermal cycling with large temperature changes. In this study, a quantitative assessment of the energy release rate has been made at the CuDB interface during temperature change finite element method (FEM). A parametric study is conducted to analyze the impact of the initial crack location and the material properties of surrounding materials. Finally, design recommendations are provided to minimize the probability of interfacial delamination in CuDB.
