A Low-Power Low-Data Rate Impulse Radio Ultra-Wideband (IR-UWB) Transmitter

2017 ◽  
Vol 26 (03) ◽  
pp. 1740013 ◽  
Author(s):  
Ifana Mahbub ◽  
Samira Shamsir ◽  
Syed K. Islam
Keyword(s):  
Low Power ◽  
Biomedical Application ◽  
Short Pulse ◽  
Impulse Radio ◽  
Data Rate ◽  
Ultra Wideband ◽  
Modulation Scheme ◽  
Sleep Mode ◽  
Operating Voltage ◽  
5 Ghz

A low-power and low-data-rate (100 kbps) fully integrated CMOS impulse radio ultra-wideband (IR-UWB) transmitter for biomedical application is presented in this paper. The transmitter is designed using a standard 180-nm CMOS technology that operates at the 3.1-5 GHz frequency range with more than 500 MHz of channel bandwidth. Modulation scheme of this transmitter is based on on-off keying (OOK) in which a short pulse represents binary “1” and absence of a pulse represents binary “0” transmission. During the ‘off’ state (sleep mode) the transmitter consumes only 0.4 μW of power for an operating voltage of 1.8 V while during the impulse transmission state it consumes a power of 36.29 μW. A pulse duration of about 3.5 ns and a peak amplitude of the frequency spectrum of about -47.8 dBm/MHz are obtained in the simulation result which fully complies with Federal Communication Commission (FCC) regulation.

scholarly journals A reconfigurable software defined ultra-wideband impulse radio transceiver

2010 ◽  
Vol 8 ◽  
pp. 67-73 ◽  
Author(s):  
M. D. Blech ◽  
A. T. Ott ◽  
P. Neumeier ◽  
M. Möller ◽  
T. F. Eibert
Keyword(s):  
Software Defined Radio ◽  
Matched Filter ◽  
Digital Signal ◽  
Impulse Radio ◽  
Ultra Wideband ◽  
Modulation Scheme ◽  
Digital To Analog Converter ◽  
Shift Keying ◽  
Reconfigurable Software ◽  
Radio Transceiver

Abstract. An ultra-wideband (UWB) software defined radio (SDR) implementation is presented. The developed impulse radio (IR) transceiver employs first order bandpass (BP) sampling at a conversion frequency which is four times the channel bandwidth. The subsampling architecture directly provides the RF signal avoiding any non-ideal mixer stages and reduces the requirements of digital signal processing implemented in a field programmable gate array (FPGA). The transmitter consists basically of a multi-Nyquist digital to analog converter (DAC), whereas the implemented matched filter (MF) receiver prototype employs a standard digitizing oscilloscope. This design can be adaptively reconfigured in terms of modulation, data rate, and channel equalization. The reconfigurable design is used for an extensive performance analysis of the quadrature phase shift keying (QPSK) modulation scheme investigating the influence of different antennas, amplifiers, narrowband interferers as well as different equalizer lengths. Even for distances up to 7 m in a multipath environment robust communication was achieved.

scholarly journals A Novel 8T Cell-Based Subthreshold Static RAM for Ultra-Low Power Platform Applications

Electronics ◽  
2020 ◽  
Vol 9 (6) ◽  
pp. 928 ◽  
Author(s):  
Taehoon Kim ◽  
Sivasundar Manisankar ◽  
Yeonbae Chung
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Cost Effective ◽  
Operating Mode ◽  
Sleep Mode ◽  
Cmos Process ◽  
Operating Voltage ◽  
Cross Point ◽  
Ultra Low Power ◽  
Static Ram

Subthreshold SRAMs profit various energy-constrained applications. The traditional 6T SRAMs exhibit poor cell stability with voltage scaling. To this end, several 8T to 16T cell designs have been reported to improve the stability. However, they either suffer one of disturbances or consume large bit-area overhead. Furthermore, some cell options have a limited write-ability. This paper presents a novel 8T static RAM for reliable subthreshold operation. The cell employs a fully differential scheme and features cross-point access. An adaptive cell bias for each operating mode eliminates the read disturbance and enlarges the write-ability as well as the half-select stability in a cost-effective small bit-area. The bit-cell also can support efficient bit-interleaving. To verify the SRAM technique, a 32-kbit macro incorporating the proposed cell was implemented with an industrial 180 nm low-power CMOS process. At 0.4 V and room temperature, the proposed cell achieves 3.6× better write-ability and 2.6× higher dummy-read stability compared with the commercialized 8T cell. The 32-kbit SRAM successfully operates down to 0.21 V (~0.27 V lower than transistor threshold voltage). At its lowest operating voltage, the sleep-mode leakage power of entire SRAM is 7.75 nW. Many design results indicate that the proposed SRAM design, which is applicable to an aggressively-scaled process, might be quite useful in realizing cost-effective robust ultra-low voltage SRAMs.

A linear, ultra wideband, low-power, 2.1-5 GHz, VCO

2010 ◽  
pp. n/a-n/a ◽  
Author(s):  
Athanasios Tsitouras ◽  
Fotis Plessas ◽  
Grigorios Kalivas
Keyword(s):  
Low Power ◽  
Ultra Wideband ◽  
5 Ghz

A low-power digitally programmable impulse radio ultra wideband transmitter with pulse shape control

2012 ◽  
Author(s):  
Anh-kiet Vuong ◽  
Alexandre Desmarais ◽  
Anis Bounif ◽  
Dominic Deslandes ◽  
Frederic Nabki
Keyword(s):  
Low Power ◽  
Pulse Shape ◽  
Shape Control ◽  
Impulse Radio ◽  
Ultra Wideband ◽  
Digitally Programmable

Low Power Digital Baseband for Impulse Radio Ultra-Wideband Transceiver

2010 ◽  
Vol 31 (1) ◽  
pp. 223-235 ◽  
Author(s):  
Wei Da Toh ◽  
Yuanjin Zheng ◽  
Chun-Huat Heng
Keyword(s):  
Low Power ◽  
Impulse Radio ◽  
Ultra Wideband ◽  
Digital Baseband
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