Reconfigurable Hardware Generation of Multigrid Solvers with Conjugate Gradient Coarse-Grid Solution

2018 ◽  
Vol 28 (04) ◽  
pp. 1850016 ◽  
Author(s):  
Christian Schmitt ◽  
Moritz Schmid ◽  
Sebastian Kuckuk ◽  
Harald Köstler ◽  
Jürgen Teich ◽  
...  
Keyword(s):  
Conjugate Gradient ◽  
Graphics Processing Units ◽  
High Performance ◽  
Central Processing ◽  
Domain Specific ◽  
Multigrid Solvers ◽  
Field Programmable ◽  
Grid Solution ◽  
Tool Set ◽  
Numerical Solver

Not only in the field of high-performance computing (HPC), field programmable gate arrays (FPGAs) are a soaringly popular accelerator technology. However, they use a completely different programming paradigm and tool set compared to central processing units (CPUs) or even graphics processing units (GPUs), adding extra development steps and requiring special knowledge, hindering widespread use in scientific computing. To bridge this programmability gap, domain-specific languages (DSLs) are a popular choice to generate low-level implementations from an abstract algorithm description. In this work, we demonstrate our approach for the generation of numerical solver implementations based on the multigrid method for FPGAs from the same code base that is also used to generate code for CPUs using a hybrid parallelization of MPI and OpenMP. Our approach yields in a hardware design that can compute up to 11 V-cycles per second with an input grid size of 4096[Formula: see text]4096 and solution on the coarsest using the conjugate gradient (CG) method on a mid-range FPGA, beating vectorized, multi-threaded execution on an Intel Xeon processor.

scholarly journals The VOLNA-OP2 tsunami code (version 1.5)

2018 ◽  
Vol 11 (11) ◽  
pp. 4621-4635 ◽  
Author(s):  
Istvan Z. Reguly ◽  
Daniel Giles ◽  
Devaraj Gopinathan ◽  
Laure Quivy ◽  
Joakim H. Beck ◽  
...  
Keyword(s):  
Graphics Processing Units ◽  
High Performance ◽  
Shallow Water Equation ◽  
Xeon Phi ◽  
Intel Xeon Phi ◽  
Central Processing ◽  
Domain Specific ◽  
Computing Platforms ◽  
Graphics Processing ◽  
Intel Xeon

Abstract. In this paper, we present the VOLNA-OP2 tsunami model and implementation; a finite-volume non-linear shallow-water equation (NSWE) solver built on the OP2 domain-specific language (DSL) for unstructured mesh computations. VOLNA-OP2 is unique among tsunami solvers in its support for several high-performance computing platforms: central processing units (CPUs), the Intel Xeon Phi, and graphics processing units (GPUs). This is achieved in a way that the scientific code is kept separate from various parallel implementations, enabling easy maintainability. It has already been used in production for several years; here we discuss how it can be integrated into various workflows, such as a statistical emulator. The scalability of the code is demonstrated on three supercomputers, built with classical Xeon CPUs, the Intel Xeon Phi, and NVIDIA P100 GPUs. VOLNA-OP2 shows an ability to deliver productivity as well as performance and portability to its users across a number of platforms.

Heterogenous Computing on Iris Matching with OpenCL

2016 ◽  
Vol 850 ◽  
pp. 129-135
Author(s):  
Buğra Şimşek ◽  
Nursel Akçam
Keyword(s):  
Graphics Processing Units ◽  
Iris Recognition ◽  
Heterogeneous Computing ◽  
Hamming Distance ◽  
Heterogeneous Systems ◽  
Digital Signal ◽  
Mobile Platforms ◽  
Central Processing ◽  
Field Programmable ◽  
Graphics Processing

This study presents parallelization of Hamming Distance algorithm, which is used for iris comparison on iris recognition systems, for heterogeneous systems that can be included Central Processing Units (CPUs), Graphics Processing Units (GPUs), Digital Signal Processing (DSP) boards, Field Programmable Gate Array (FPGA) and some other mobile platforms with OpenCL. OpenCL allows to run same code on CPUs, GPUs, FPGAs and DSP boards. Heterogeneous computing refers to systems include different kind of devices (CPUs, GPUs, FPGAs and other accelerators). Heterogeneous computing gains performance or reduces power for suitable algorithms on these OpenCL supported devices. In this study, Hamming Distance algorithm has been coded with C++ as a sequential code and has been parallelized a designated method by us with OpenCL. Our OpenCL code has been executed on Nvidia GT430 GPU and Intel Xeon 5650 processor. The OpenCL code implementation demonstrates that speed up to 87 times with parallelization. Also our study differs from other studies, which accelerate iris matching, with regard to ensure heterogeneous computing by using OpenCL.

scholarly journals State-of-the-art in Heterogeneous Computing

2010 ◽  
Vol 18 (1) ◽  
pp. 1-33 ◽  
Author(s):  
Andre R. Brodtkorb ◽  
Christopher Dyken ◽  
Trond R. Hagen ◽  
Jon M. Hjelmervik ◽  
Olaf O. Storaasli
Keyword(s):  
Graphics Processing Units ◽  
High Performance ◽  
Heterogeneous Computing ◽  
State Of The Art ◽  
Peak Performance ◽  
Fine Grained ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Cost Efficient ◽  
Graphics Processing

Node level heterogeneous architectures have become attractive during the last decade for several reasons: compared to traditional symmetric CPUs, they offer high peak performance and are energy and/or cost efficient. With the increase of fine-grained parallelism in high-performance computing, as well as the introduction of parallelism in workstations, there is an acute need for a good overview and understanding of these architectures. We give an overview of the state-of-the-art in heterogeneous computing, focusing on three commonly found architectures: the Cell Broadband Engine Architecture, graphics processing units (GPUs), and field programmable gate arrays (FPGAs). We present a review of hardware, available software tools, and an overview of state-of-the-art techniques and algorithms. Furthermore, we present a qualitative and quantitative comparison of the architectures, and give our view on the future of heterogeneous computing.

scholarly journals Controllers: An abstraction to ease the use of hardware accelerators

2017 ◽  
Vol 32 (6) ◽  
pp. 838-853 ◽  
Author(s):  
Ana Moreton–Fernandez ◽  
Hector Ortega–Arranz ◽  
Arturo Gonzalez–Escribano
Keyword(s):  
Graphics Processing Units ◽  
High Performance ◽  
Abstract Entity ◽  
Hardware Accelerators ◽  
Processing Unit ◽  
Central Processing ◽  
Computing Platforms ◽  
Graphics Processing ◽  
Performance Computing ◽  
Selection Of

Nowadays the use of hardware accelerators, such as the graphics processing units or XeonPhi coprocessors, is key in solving computationally costly problems that require high performance computing. However, programming solutions for an efficient deployment for these kind of devices is a very complex task that relies on the manual management of memory transfers and configuration parameters. The programmer has to carry out a deep study of the particular data that needs to be computed at each moment, across different computing platforms, also considering architectural details. We introduce the controller concept as an abstract entity that allows the programmer to easily manage the communications and kernel launching details on hardware accelerators in a transparent way. This model also provides the possibility of defining and launching central processing unit kernels in multi-core processors with the same abstraction and methodology used for the accelerators. It internally combines different native programming models and technologies to exploit the potential of each kind of device. Additionally, the model also allows the programmer to simplify the proper selection of values for several configuration parameters that can be selected when a kernel is launched. This is done through a qualitative characterization process of the kernel code to be executed. Finally, we present the implementation of the controller model in a prototype library, together with its application in several case studies. Its use has led to reductions in the development and porting costs, with significantly low overheads in the execution times when compared to manually programmed and optimized solutions which directly use CUDA and OpenMP.

scholarly journals POM.gpu-v1.0: a GPU-based Princeton Ocean Model

2015 ◽  
Vol 8 (9) ◽  
pp. 2815-2827 ◽  
Author(s):  
S. Xu ◽  
X. Huang ◽  
L.-Y. Oey ◽  
F. Xu ◽  
H. Fu ◽  
...  
Keyword(s):  
Graphics Processing Units ◽  
High Performance ◽  
Climate Models ◽  
Ocean Model ◽  
Compute Unified Device Architecture ◽  
Princeton Ocean Model ◽  
Central Processing ◽  
Device Architecture ◽  
Computationally Intensive ◽  
Graphics Processing

Abstract. Graphics processing units (GPUs) are an attractive solution in many scientific applications due to their high performance. However, most existing GPU conversions of climate models use GPUs for only a few computationally intensive regions. In the present study, we redesign the mpiPOM (a parallel version of the Princeton Ocean Model) with GPUs. Specifically, we first convert the model from its original Fortran form to a new Compute Unified Device Architecture C (CUDA-C) code, then we optimize the code on each of the GPUs, the communications between the GPUs, and the I / O between the GPUs and the central processing units (CPUs). We show that the performance of the new model on a workstation containing four GPUs is comparable to that on a powerful cluster with 408 standard CPU cores, and it reduces the energy consumption by a factor of 6.8.

scholarly journals High-performance computing in water resources hydrodynamics

2020 ◽  
Vol 22 (5) ◽  
pp. 1217-1235 ◽  
Author(s):  
M. Morales-Hernández ◽  
M. B. Sharif ◽  
S. Gangrade ◽  
T. T. Dullo ◽  
S.-C. Kao ◽  
...  
Keyword(s):  
Water Resources ◽  
High Performance Computing ◽  
Graphics Processing Units ◽  
High Performance ◽  
Large Scale ◽  
Test Case ◽  
Processing Unit ◽  
Central Processing ◽  
Graphics Processing ◽  
Performance Computing

Abstract This work presents a vision of future water resources hydrodynamics codes that can fully utilize the strengths of modern high-performance computing (HPC). The advances to computing power, formerly driven by the improvement of central processing unit processors, now focus on parallel computing and, in particular, the use of graphics processing units (GPUs). However, this shift to a parallel framework requires refactoring the code to make efficient use of the data as well as changing even the nature of the algorithm that solves the system of equations. These concepts along with other features such as the precision for the computations, dry regions management, and input/output data are analyzed in this paper. A 2D multi-GPU flood code applied to a large-scale test case is used to corroborate our statements and ascertain the new challenges for the next-generation parallel water resources codes.

uBlasCL: Architecture Agnostic Massively Parallel Linear Algebra System

2011 ◽  
Author(s):  
Athanasios Iliopoulos ◽  
John G. Michopoulos
Keyword(s):  
Linear Algebra ◽  
Graphics Processing Units ◽  
Processing System ◽  
Performance Testing ◽  
General Purpose ◽  
Massively Parallel ◽  
Domain Specific Languages ◽  
Central Processing ◽  
Domain Specific ◽  
Graphics Processing

The need for more efficient, more abstract and easier to use parallel programming interfaces has been recently intensified with the introduction and remarkable evolution of technologies such as the General Purpose Graphics Processing Units (GPG-PUs) and multi-core Central Processing Units (CPUs). In the present paper we present the introduction of the uBlasCL system as a Domain Specific Embedded Language within C++ that implements a Basic Linear Algebra Interface for OpenCL. The system is architecture agnostic, in the sense that it can be programmed independently of the targeted architecture, is massively parallel, and achieves efficiency that tracks well the increase in hardware performance advances. Our effort is based on the utilization of template metaprogramming and domain specific languages fundamentals, for developing a system that has the syntactic flexibility of a symbolic term processing system for expressing mathematics, and the semantic and executional power to exploit the parallelism offered by the hardware in an automated, transparent to the user, and efficiently mapped on the hardware manner. We also describe its relation to C++, template programming, domain specific languages and OpenCL. In the effort to develop uBlasCL we also developed a middleware library named CL++, as a convenient C++ interface to OpenCL. After the architectural and the implementation descriptions of the system, we present performance testing results demonstrating its potential power.

High-Performance Image Reconstruction (HPIR) in Three Dimensions

2010 ◽  
pp. 121-162
Author(s):  
Olivier Bockenbach ◽  
Michael Knaup ◽  
Sven Steckmann ◽  
Marc Kachelrieß
Keyword(s):  
Image Reconstruction ◽  
Graphics Processing Units ◽  
High Performance ◽  
Three Dimensions ◽  
Ct Reconstruction ◽  
Reconstruction Algorithms ◽  
Destructive Testing ◽  
Processing Power ◽  
Field Programmable ◽  
The Way

Commonly used in medical imaging for diagnostic purposes, in luggage scanning, as well as in industrial non-destructive testing applications, Computed Tomography (CT) is an imaging technique that provides cross sections of an object from measurements taken from different angular positions around the object. CT, also referred to as Image Reconstruction (IR), is known to be a very compute-intensive problem. In its simplest form, the computational load is a function of O(M × N3), where M represents the number of measurements taken around the object and N is the dimension of the object. Furthermore, research institutes report that the increase in processing power required by CT is consistently above Moore‘s Law. On the other hand, the changing work flow in hospital requires obtaining CT images faster with better quality from lower dose. In some cases, real time is needed. High Performance Image Reconstruction (HPIR) has to be used to match the performance requirements involved by the use of modern CT reconstruction algorithms in hospitals. Traditionally, this problem had been solved by the design of specific hardware. Nowadays, the evolution of technology makes it possible to use Components of the Shelf (COTS). Typical HPIR platforms can be built around multicore processors such as the Cell Broadband Engine (CBE), General-Purpose Graphics Processing Units (GPGPU) or Field Programmable Gate Arrays (FPGA). These platforms exhibit different level in the parallelism required to implement CT reconstruction algorithms. They also have different properties in the way the computation can be carried out, potentially requiring drastic changes in the way an algorithm can be implemented. Furthermore, because of their COTS nature, it is not always easy to take the best advantages of a given platform and compromises have to be made. Finally, a fully fleshed reconstruction platform also includes the data acquisition interface as well as the vizualisation of the reconstructed slices. These parts are the area of excellence of FPGAs and GPGPUs. However, more often then not, the processing power available in those units exceeds the requirement of a given pipeline and the remaining real estate and processing power can be used for the core of the reconstruction pipeline. Indeed, several design options can be considered for a given algorithm with yet another set of compromises.

scholarly journals Parallelizing Multiple Flow Accumulation Algorithm using CUDA and OpenACC

2019 ◽  
Vol 8 (9) ◽  
pp. 386 ◽  
Author(s):  
Natalija Stojanovic ◽  
Dragan Stojanovic
Keyword(s):  
Energy Consumption ◽  
Graphics Processing Units ◽  
High Performance ◽  
Programming Model ◽  
Flow Direction ◽  
Computing Methods ◽  
Terrain Analysis ◽  
Central Processing ◽  
Watershed Analysis ◽  
Programming Effort

Watershed analysis, as a fundamental component of digital terrain analysis, is based on the Digital Elevation Model (DEM), which is a grid (raster) model of the Earth surface and topography. Watershed analysis consists of computationally and data intensive computing algorithms that need to be implemented by leveraging parallel and high-performance computing methods and techniques. In this paper, the Multiple Flow Direction (MFD) algorithm for watershed analysis is implemented and evaluated on multi-core Central Processing Units (CPU) and many-core Graphics Processing Units (GPU), which provides significant improvements in performance and energy usage. The implementation is based on NVIDIA CUDA (Compute Unified Device Architecture) implementation for GPU, as well as on OpenACC (Open ACCelerators), a parallel programming model, and a standard for parallel computing. Both phases of the MFD algorithm (i) iterative DEM preprocessing and (ii) iterative MFD algorithm, are parallelized and run over multi-core CPU and GPU. The evaluation of the proposed solutions is performed with respect to the execution time, energy consumption, and programming effort for algorithm parallelization for different sizes of input data. An experimental evaluation has shown not only the advantage of using OpenACC programming over CUDA programming in implementing the watershed analysis on a GPU in terms of performance, energy consumption, and programming effort, but also significant benefits in implementing it on the multi-core CPU.

scholarly journals A TensorFlow Extension Framework for Optimized Generation of Hardware CNN Inference Engines

Technologies ◽  
2020 ◽  
Vol 8 (1) ◽  
pp. 6 ◽  
Author(s):  
Vasileios Leon ◽  
Spyridon Mouselinos ◽  
Konstantina Koliogeorgi ◽  
Sotirios Xydis ◽  
Dimitrios Soudris ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
High Performance ◽  
Graphics Processing Unit ◽  
Inference Engine ◽  
Efficient Solutions ◽  
Processing Unit ◽  
Central Processing ◽  
Inference Engines ◽  
Field Programmable ◽  
Hardware Description

The workloads of Convolutional Neural Networks (CNNs) exhibit a streaming nature that makes them attractive for reconfigurable architectures such as the Field-Programmable Gate Arrays (FPGAs), while their increased need for low-power and speed has established Application-Specific Integrated Circuit (ASIC)-based accelerators as alternative efficient solutions. During the last five years, the development of Hardware Description Language (HDL)-based CNN accelerators, either for FPGA or ASIC, has seen huge academic interest due to their high-performance and room for optimizations. Towards this direction, we propose a library-based framework, which extends TensorFlow, the well-established machine learning framework, and automatically generates high-throughput CNN inference engines for FPGAs and ASICs. The framework allows software developers to exploit the benefits of FPGA/ASIC acceleration without requiring any expertise on HDL development and low-level design. Moreover, it provides a set of optimization knobs concerning the model architecture and the inference engine generation, allowing the developer to tune the accelerator according to the requirements of the respective use case. Our framework is evaluated by optimizing the LeNet CNN model on the MNIST dataset, and implementing FPGA- and ASIC-based accelerators using the generated inference engine. The optimal FPGA-based accelerator on Zynq-7000 delivers 93% less memory footprint and 54% less Look-Up Table (LUT) utilization, and up to 10× speedup on the inference execution vs. different Graphics Processing Unit (GPU) and Central Processing Unit (CPU) implementations of the same model, in exchange for a negligible accuracy loss, i.e., 0.89%. For the same accuracy drop, the 45 nm standard-cell-based ASIC accelerator provides an implementation which operates at 520 MHz and occupies an area of 0.059 mm 2 , while the power consumption is ∼7.5 mW.

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