OPTIMAL SYNTHESIS OF PROCESSOR ARRAYS WITH PIPELINED ARITHMETIC UNITS

1994 ◽  
Vol 04 (03) ◽  
pp. 339-350
Author(s):  
KUMAR GANAPATHY ◽  
BENJAMIN W. WAH
Keyword(s):  
Design Method ◽  
Parameter Method ◽  
Systematic Design ◽  
Processing Elements ◽  
Processor Arrays ◽  
Data Flows ◽  
Matrix Products ◽  
Efficient Scheme ◽  
General Parameter ◽  
Additional Constraints

Two-level pipelining in processor arrays (PAs) involves pipelining of operations across processing elements (PEs) and pipelining of operations in functional units in each PE. Although it is an attractive method for improving the throughput of PAs, existing methods for generating PAs with two-level pipelining are restricted and cannot systematically explore the entire space of feasible designs. In this paper, we extend a systematic design method, called General Parameter Method (GPM), we have developed earlier to find optimal designs of PAs with two-level pipelines. The basic idea is to add new constraints on periods of data flows to include the effect of internal functional pipelines in the PEs. As an illustration, we present pipelined PA designs for computing matrix products. For n-dimensional meshes and other symmetric problems, we provide an efficient scheme to obtain a pipelined PA from a non-pipelined PA using a reindexing transformation. This scheme is used in GPM as a pruning condition to arrive at optimal pipelined PAs efficiently. For pipelines with minimum initiation interval (MII) greater than unity, we show additional constraints that ensure correctness of the synthesized PAs.

Topology Optimization for Design of Origami-Based Active Mechanisms

2014 ◽  
Author(s):  
Kazuko Fuchi ◽  
Philip R. Buskohl ◽  
James J. Joo ◽  
Gregory W. Reich ◽  
Richard A. Vaia
Keyword(s):  
Topology Optimization ◽  
Mechanism Design ◽  
Design Method ◽  
Truss Structures ◽  
Systematic Design ◽  
Design Strategies ◽  
Foldable Structures ◽  
And Performance ◽  
2D And 3D ◽  
Additional Constraints

Origami structures morph between 2D and 3D conformations along predetermined fold lines that efficiently program the form of the structure and show potential for many engineering applications. However, the enormity of the design space and the complex relationship between origami-based geometries and engineering metrics place a severe limitation on design strategies based on intuition. The presented work proposes a systematic design method using topology optimization to distribute foldline properties within a reference crease pattern, adding or removing folds through optimization, for a mechanism design. Following the work of Schenk and Guest, foldable structures are modeled as pin-joint truss structures with additional constraints on fold, or dihedral, angles. The performance of a designed origami mechanism is evaluated in 3D by applying prescribed forces and finding displacements at set locations. The integration of the concept of origami in mechanism design thus allows for the description of designs in 2D and performance in 3D. Numerical examples indicate that origami mechanisms with desired deformations can be obtained using the proposed method. A constraint on the number of foldlines is used to simplify a design.

Systematic Design Method for Information Modeling in CAD/CAE

2003 ◽  
Author(s):  
Sai Zeng ◽  
Edward J. Kim ◽  
Gregory M. Mocko ◽  
Angran Xiao ◽  
Russell Peak ◽  
...  
Keyword(s):  
Solid Mechanics ◽  
Design Method ◽  
Building Blocks ◽  
Information Model ◽  
Information Modeling ◽  
Systematic Design ◽  
Element Analysis ◽  
Design Models ◽  
Information Models ◽  
Analysis Models

As engineering systems are increasingly becoming more complex, the need for information models is growing accordingly. Extensive research is currently underway to develop engineering data management capabilities and to understand the role of information as a systems integrator. In order to develop information models more effectively, a systematic methodology is needed to better manage data and develop information models. In the area of CAD/CAE/CAM applications, an information gap exists between design models and analysis models. To this end, a multi-representational architecture (MRA) is presented to facilitate the transformation of information from design models to various support analysis models. In this paper, our primary focus is on ABBs (Analysis Building Blocks) for solid mechanics and thermal systems that generate FEA (Finite Element Analysis) SMMs (Solution Method Models) to obtain their results. Our focus in this paper is to investigate the effectiveness of the Pahl and Beitz methodology in developing the ABB information model. The Pahl and Beitz design methodology is intended for physical product design applications. Three of the four phases of the Pahl and Beitz methodology are examined and modified to facilitate development of the ABB information model. The augmentations of these phases are presented in this paper. The results of the development of concepts of ABB information model using the Pahl and Beitz methodology support the use of systematic design methodologies for the development of information models. The emphasis of this work is on the methodology used to develop the ABB information model rather than the technical result of the ABB model.

Transformable Electronics Implantation in ROM for Anti-Reverse Engineering

2019 ◽  
Vol 28 (03n04) ◽  
pp. 1940021
Author(s):  
Shuai Chen ◽  
Lei Wang
Keyword(s):  
Integrated Circuits ◽  
Reverse Engineering ◽  
Lower Cost ◽  
Design Method ◽  
Data Extraction ◽  
Semiconductor Industry ◽  
Physical Structure ◽  
Security And Privacy ◽  
Systematic Design ◽  
Non Volatile Memory

The protection of intellectual property (IP) is increasingly critical for IP vendors in the semiconductor industry. Read Only Memories (ROMs) serve as important non-volatile memory in various hardware systems to store predefined data and programs, which is critical to IP protection. Its pre-determined layout pattern makes unauthorized data extraction through chip-level reverse engineering easy to carry out. Advanced reverse engineering techniques can physically disassemble the chip and derive the IPs precisely at a much lower cost than the value of IP design that chips carry. This invasive hardware attack obtaining information from IC chips always violates the IP rights of vendors. This paper proposes a new security mechanism implanted ROM design to address the vulnerability to reverse energy attacks. Irreversible via in ROM layout transform triggered by reverse engineering completely changes the electrical properties and the physical structure of ROMs that determine the stored data. Newly-created patten will significantly increase the difficulty of reverse engineering, even lead the attackers to another working function mode. Furthermore, to improve the effectiveness of the proposed technique, a systematic design method is developed targeting integrated circuits with multiple design constraints. Two widely used ROM scheme cases have been studied to test the design method and its effectiveness. Simulations have been conducted to demonstrate the capability of the proposed technique, which generates extremely large complexity for reverse engineering with manageable overhead. CCS Concepts: Security and privacy → Hardware reverse engineering; Hardware → Hard and soft IP

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