A High Linear CMOS Body Effect Compensation Bootstrapped Switch

2015 ◽  
Vol 24 (03) ◽  
pp. 1550032 ◽  
Author(s):  
Siwan Dong ◽  
Minjie Liu ◽  
Zhangming Zhu ◽  
Yintang Yang
Keyword(s):  
High Speed ◽  
Dynamic Range ◽  
Harmonic Distortion ◽  
Cmos Process ◽  
Body Effect ◽  
Spurious Free Dynamic Range ◽  
Source Voltage ◽  
Bootstrapped Switch ◽  
Free Dynamic ◽  
Better Than

This paper presents a new bootstrapped switch with high speed and low nonlinear distortion. Instead of fixed voltage, the gate-to-source voltage of switch varies with input to implement first-order body effect compensation. Post-layout simulations have been done in standard 0.18-μm CMOS process at 1.8 V, and results indicate that at 200 MHz sample rate, a peak signal-to-noise-and-distortion ratio (SNDR) of 98.4 dB, spurious-free dynamic range (SFDR) of 105.7 dB and total harmonic distortion (THD) of -104.9 dB can be acquired. For input frequency up to the 60 MHz frequency, proposed structure maintains |THD| over 85 dB, SFDR better than 86 dB, respectively.

Synergy Micro-Electronics Technology with a High Linearity BiCMOS Sample-and-Hold Circuit

2013 ◽  
Vol 473 ◽  
pp. 50-53
Author(s):  
Jie Lin ◽  
Fei Yan Mu
Keyword(s):  
Dynamic Range ◽  
Harmonic Distortion ◽  
High Accuracy ◽  
Pipeline Adc ◽  
Nonlinearity Error ◽  
Front End ◽  
Sample And Hold ◽  
Spurious Free Dynamic Range ◽  
Bicmos Process ◽  
Free Dynamic

A high accuracy BiCMOS sample and hold (S/H) circuit employed in the front end of a12bit 10 MS/s Pipeline ADC is presented. To reduce the nonlinearity error cause by the sampling switch, a signal dependent clock bootstrapping system is introduced. It is implemented using 0.6 um BiCMOS process. An 88.77 dB spurious-free dynamic range (SFDR), and a -105.20 dB total harmonic distortion (THD) are obtained.

scholarly journals A 3GSps 12-bit Four-Channel Time-Interleaved Pipelined ADC in 40 nm CMOS Process

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1551 ◽  
Author(s):  
Jianwen Li ◽  
Xuan Guo ◽  
Jian Luan ◽  
Danyu Wu ◽  
Lei Zhou ◽  
...  
Keyword(s):  
Dynamic Range ◽  
Cmos Process ◽  
Pipelined Adc ◽  
Least Significant Bit ◽  
Analog To Digital ◽  
Capacitor Mismatch ◽  
Gain Error ◽  
Spurious Free Dynamic Range ◽  
Time Interleaved ◽  
Free Dynamic

This paper presents a four-channel time-interleaved 3GSps 12-bit pipelined analog-to-digital converter (ADC). The combination of master clock sampling and delay-adjusting is adopted to remove the time skew due to channel mismatches. An early comparison scheme is used to minimize the non-overlapping time, where a custom-designed latch is developed to replace the typical non-overlapping clock generator. By using the dither capacitor to generate an equivalent direct current input, a zero-input-based calibration is developed to correct the capacitor mismatch and inter-stage gain error. Fabricated in a 40 nm CMOS process, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 57.8 dB and a spurious free dynamic range (SFDR) of 72 dB with a 23 MHz input tone. It can achieve an SNDR above 52.3 dB and an SFDR above 61.5 dB across the entire first Nyquist zone. The differential and integral nonlinearities are −0.93/+0.73 least significant bit (LSB) and −2.8/+4.3 LSB, respectively. The ADC consumes 450 mW powered at 1.8V, occupies an active area of 3 mm × 1.3 mm. The calculated Walden figure of merit reaches 0.44 pJ/step.

System-Level Mitigation of Undersampling ADC Nonlinearity for High-IF Radio Receivers

Frequenz ◽  
2012 ◽  
Vol 66 (9-10) ◽  
Author(s):  
Georg Vallant ◽  
Michael Epp ◽  
Markus Allén ◽  
Mikko Valkama ◽  
Friedrich K. Jondral
Keyword(s):  
Software Defined Radio ◽  
High Speed ◽  
Dynamic Range ◽  
System Level ◽  
General Validity ◽  
Radio Receivers ◽  
Rf Signals ◽  
Spurious Free Dynamic Range ◽  
Digital Linearization ◽  
Free Dynamic

AbstractOver the last years ongoing advances in ADC technology have enabled RF signals to be sampled at IF frequencies. Undersampling is nowadays employed in software-defined radio or radar receivers and offers the possibility to relieve requirements in the analog receiver partition. Unfortunately, when moving to higher IF concepts, this becomes demanding for the ADC itself, because of inherent spurious-free dynamic range (SFDR) roll-off that increases with input frequency. This fact often limits the receiver's IF placement to Nyquist zone (NZ) 2. In this work the emerging concept of Digital Assistance is pursued to give the receiver access to higher NZs while making no compromise on the SFDR. We will present and discuss post-correction results for two 16-bit high-speed converters from two different vendors at 120 and 125 MSPS, respectively. The proposed system-level post-correction decomposes nonlinearity into a static and a dynamic part. For both ADCs under investigation the degraded SFDR in higher NZs could be improved by up to 15 dB using purely digital linearization technologies, thus increasing the detectability of small signals in the presence of very strong signals or interferers. Near-identical results for both ADCs confirm the general validity of the system-level correction approach.

NEW SAMPLING METHOD TO IMPROVE THE SFDR OF WIDE BANDWIDTH ADC DEDICATED TO NEXT GENERATION WIRELESS TRANSCEIVER

2004 ◽  
Vol 13 (06) ◽  
pp. 1183-1201
Author(s):  
KAMAL EL-SANKARY ◽  
ALI ASSI ◽  
MOHAMAD SAWAN
Keyword(s):  
High Speed ◽  
Sampling Method ◽  
Dynamic Range ◽  
Sampling Rate ◽  
Analog To Digital ◽  
Wireless Transceiver ◽  
Spurious Free Dynamic Range ◽  
Interleaved Adc ◽  
Time Interleaved ◽  
Free Dynamic

Modern wireless communication standards that support high rates of voice and video streaming need high-speed Analog-to-Digital Converters (ADCs) with wide Spurious-Free Dynamic Range (SFDR). Conventional time-interleaved ADCs suffer from spurious components that seriously affect the SFDR. In this paper, we present the mathematical background describing the effect of randomizing the samples among the interleaved ADCs and we propose a digitally oriented method based on this analysis to randomize the mismatches among the ADC channels. Analyses and simulations show the effectiveness of the proposed approach in multi-channel ADCs with arbitrary bit resolution, channel's number and sampling rate. For a 10-bit 500 MS/s ADC, the SFDR achieved using the proposed randomizing method can be as wide as 75 dB, which is an enhancement of more than 26 dB comparing to the conventional time interleaved ADC.

CHARACTERIZING THE PERFORMANCE OF A HIGH-SPEED ADC FOR THE SMA DIGITAL BACKEND

2014 ◽  
Vol 03 (01) ◽  
pp. 1450001 ◽  
Author(s):  
N. A. PATEL ◽  
R. W. WILSON ◽  
R. PRIMIANI ◽  
J. WEINTROUB ◽  
J. TEST ◽  
...  
Keyword(s):  
High Speed ◽  
Dynamic Range ◽  
Single Channel ◽  
Noise Power ◽  
Response Signal ◽  
Analog To Digital ◽  
High Speed Adc ◽  
Spurious Free Dynamic Range ◽  
Channel Mode ◽  
Free Dynamic

We report on tests of a 5 Gs/s analog-to-digital converter (ADC) used in the new Submillimeter Array (SMA) Digital Backend (DBE). The ADC is e2v EV8AQ160, with 8-bit resolution and 4 interleaved cores, operated in single-channel mode. We measured the frequency response, Signal to Noise and Distortion (SINAD), Spurious Free Dynamic Range (SFDR), Noise Power Ratio and intermodulation distortion over the bandwidth of 2.25 GHz. The performance of this ADC is found to be adequate for our application in the SMA DBE. We describe the procedure of aligning the four cores for adjustments of offset, gain and phase parameters which improve the performance of the ADC, particularly in SINAD and SFDR.

scholarly journals A 12-bit 40-MS/s SAR ADC with Calibration-Less Switched Capacitive Reference Driver

Electronics ◽  
2020 ◽  
Vol 9 (11) ◽  
pp. 1854
Author(s):  
Hyungyu Ju ◽  
Sewon Lee ◽  
Minjae Lee
Keyword(s):  
Dynamic Range ◽  
Supply Voltage ◽  
Voltage Drop ◽  
Sar Adc ◽  
Cmos Process ◽  
Nyquist Frequency ◽  
Digital To Analog Converter ◽  
Spurious Free Dynamic Range ◽  
Analog Converter ◽  
Free Dynamic

This paper presents a switched capacitive reference driver (SCRD) with a low-energy switching scheme. In order to reduce the performance degradation resulting from a signal-dependent voltage drop in a capacitive reference driver (CRD) without increasing the capacitance (CREF) of a CRD, the proposed SCRD utilizes the CRD for LSB conversion cycles. In MSB conversion cycles, a supply voltage is used as a reference voltage to save on area and power consumption. As such, the proposed SCRD significantly relaxes the required CREF, and does not necessitate bit weight calibration or compensation requiring an auxiliary capacitor-based digital-to-analog converter (CDAC). To evaluate the proposed SCRD, a prototype 12-bit 40-MS/s SAR ADC is fabricated in a 65 nm CMOS process. With near Nyquist frequency, the measured spurious-free dynamic range (SFDR) of the SAR ADC with the SCRD is 80.6 dB, which is about a 16 dB improvement from the SFDR of a SAR ADC with a CRD only.

scholarly journals Wideband Reconfigurable Integrated Low-Pass Filter for 5G Compatible Software Defined Radio Solutions

Electronics ◽  
2021 ◽  
Vol 10 (6) ◽  
pp. 734
Author(s):  
Karolis Kiela ◽  
Marijan Jurgo ◽  
Vytautas Macaitis ◽  
Romualdas Navickas
Keyword(s):  
Software Defined Radio ◽  
Dynamic Range ◽  
Noise Figure ◽  
Harmonic Distortion ◽  
Cmos Process ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Filter Performance ◽  
Low Pass ◽  
Bandwidth Tuning

This article presents a wideband reconfigurable integrated low-pass filter (LPF) for 5G NR compatible software-defined radio (SDR) solutions. The filter uses Active-RC topology to achieve high linearity performance. Its bandwidth can be tuned from 2.5 MHz to 200 MHz, which corresponds to a tuning ratio of 92.8. The order of the filter can be changed between the 2nd, 4th, or 6th order; it has built-in process, voltage, and temperature (PVT) compensation with a tuning range of ±42%; and power management features for optimization of the filter performance across its entire range of bandwidth tuning. Across its entire order, bandwidth, and power configuration range, the filter achieves in-band input-referred third-order intercept point (IIP3) between 32.7 dBm and 45.8 dBm, spurious free dynamic range (SFDR) between 63.6 dB and 79.5 dB, 1 dB compression point (P1dB) between 9.9 dBm and 14.1 dBm, total harmonic distortion (THD) between −85.6 dB and −64.5 dB, noise figure (NF) between 25.9 dB and 31.8 dB and power dissipation between 1.19 mW and 73.4 mW. The LPF was designed and verified using 65 nm CMOS process; it occupies a 0.429 mm2 area of silicon and uses a 1.2 V supply.

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