scholarly journals A 12-bit 40-MS/s SAR ADC with Calibration-Less Switched Capacitive Reference Driver

Electronics ◽  
2020 ◽  
Vol 9 (11) ◽  
pp. 1854
Author(s):  
Hyungyu Ju ◽  
Sewon Lee ◽  
Minjae Lee
Keyword(s):  
Dynamic Range ◽  
Supply Voltage ◽  
Voltage Drop ◽  
Sar Adc ◽  
Cmos Process ◽  
Nyquist Frequency ◽  
Digital To Analog Converter ◽  
Spurious Free Dynamic Range ◽  
Analog Converter ◽  
Free Dynamic

This paper presents a switched capacitive reference driver (SCRD) with a low-energy switching scheme. In order to reduce the performance degradation resulting from a signal-dependent voltage drop in a capacitive reference driver (CRD) without increasing the capacitance (CREF) of a CRD, the proposed SCRD utilizes the CRD for LSB conversion cycles. In MSB conversion cycles, a supply voltage is used as a reference voltage to save on area and power consumption. As such, the proposed SCRD significantly relaxes the required CREF, and does not necessitate bit weight calibration or compensation requiring an auxiliary capacitor-based digital-to-analog converter (CDAC). To evaluate the proposed SCRD, a prototype 12-bit 40-MS/s SAR ADC is fabricated in a 65 nm CMOS process. With near Nyquist frequency, the measured spurious-free dynamic range (SFDR) of the SAR ADC with the SCRD is 80.6 dB, which is about a 16 dB improvement from the SFDR of a SAR ADC with a CRD only.

Two-Dimensional Structure Compatible with DEM Methods Utilizing in DACs

2018 ◽  
Vol 27 (09) ◽  
pp. 1850142 ◽  
Author(s):  
Mehdi Bandali ◽  
Omid Hashemipour
Keyword(s):  
Dynamic Range ◽  
Cmos Technology ◽  
Dimensional Structure ◽  
Signal Frequency ◽  
Two Dimensional ◽  
Dynamic Element Matching ◽  
Digital To Analog Converter ◽  
Spurious Free Dynamic Range ◽  
Analog Converter ◽  
Free Dynamic

A two-dimensional digital-to-analog converter (DAC) structure compatible with dynamic element matching (DEM) methods is presented. Unlike the DACs using segmented structure for employing DEM, the new structure randomizes inter-segment error. This advantage is achieved because of the characteristics of the algorithm of two-dimensional decoding. The simulation results in 180[Formula: see text]nm CMOS technology, 319.72[Formula: see text]MHz signal frequency and 800[Formula: see text]MS/s sample rate for an 8-bit two-dimensional DAC utilizing the presented structure, shows 14.94[Formula: see text]dB spurious-free dynamic range (SFDR) improvement compared to the SFDR of the same DAC without employing the presented structure. Also, the IMD3 of the DAC employing the presented structure for [Formula: see text][Formula: see text]MHz and [Formula: see text][Formula: see text]MHz is 50.1[Formula: see text]dB.

A DITHERING TECHNIQUE FOR SHA_LESS PIPELINED ADC

2014 ◽  
Vol 23 (01) ◽  
pp. 1450006 ◽  
Author(s):  
NING NING ◽  
LING DU ◽  
HUA CHEN ◽  
SHUANGYI WU ◽  
QI YU ◽  
...  
Keyword(s):  
Dynamic Range ◽  
Signal To Noise Ratio ◽  
Input Voltage ◽  
Pipelined Adc ◽  
Digital To Analog Converter ◽  
Analog To Digital ◽  
Behavior Simulation ◽  
Spurious Free Dynamic Range ◽  
Analog Converter ◽  
Free Dynamic

A dithering technique for pipelined analog-to-digital converter (ADC) without sample-and-hold amplifier (SHA) is proposed in this paper. The dither signals are injected to the output of the first stage multiplying digital-to-analog converter (MDAC) and the input of the first stage Sub_ADC simultaneously. The equivalent input voltage of the first stage Sub_ADC is consistent with that of the first stage MDAC with dither. To subtract the dither signal precisely, all of the dither signals are quantified by the ADC itself before normal conversion, and the digital codes representing dither signals are stored. During normal conversion, a dither signal selected randomly is added to the analog input and the corresponding digital code is subtracted from the digital output. The proposed dithering technique is verified by behavior simulation. The simulation results show that the spurious free dynamic range (SFDR) is improved effectively and the degradation of signal-to-noise ratio (SNR) can be minimized.

scholarly journals A 3GSps 12-bit Four-Channel Time-Interleaved Pipelined ADC in 40 nm CMOS Process

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1551 ◽  
Author(s):  
Jianwen Li ◽  
Xuan Guo ◽  
Jian Luan ◽  
Danyu Wu ◽  
Lei Zhou ◽  
...  
Keyword(s):  
Dynamic Range ◽  
Cmos Process ◽  
Pipelined Adc ◽  
Least Significant Bit ◽  
Analog To Digital ◽  
Capacitor Mismatch ◽  
Gain Error ◽  
Spurious Free Dynamic Range ◽  
Time Interleaved ◽  
Free Dynamic

This paper presents a four-channel time-interleaved 3GSps 12-bit pipelined analog-to-digital converter (ADC). The combination of master clock sampling and delay-adjusting is adopted to remove the time skew due to channel mismatches. An early comparison scheme is used to minimize the non-overlapping time, where a custom-designed latch is developed to replace the typical non-overlapping clock generator. By using the dither capacitor to generate an equivalent direct current input, a zero-input-based calibration is developed to correct the capacitor mismatch and inter-stage gain error. Fabricated in a 40 nm CMOS process, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 57.8 dB and a spurious free dynamic range (SFDR) of 72 dB with a 23 MHz input tone. It can achieve an SNDR above 52.3 dB and an SFDR above 61.5 dB across the entire first Nyquist zone. The differential and integral nonlinearities are −0.93/+0.73 least significant bit (LSB) and −2.8/+4.3 LSB, respectively. The ADC consumes 450 mW powered at 1.8V, occupies an active area of 3 mm × 1.3 mm. The calculated Walden figure of merit reaches 0.44 pJ/step.

A High Linear CMOS Body Effect Compensation Bootstrapped Switch

2015 ◽  
Vol 24 (03) ◽  
pp. 1550032 ◽  
Author(s):  
Siwan Dong ◽  
Minjie Liu ◽  
Zhangming Zhu ◽  
Yintang Yang
Keyword(s):  
High Speed ◽  
Dynamic Range ◽  
Harmonic Distortion ◽  
Cmos Process ◽  
Body Effect ◽  
Spurious Free Dynamic Range ◽  
Source Voltage ◽  
Bootstrapped Switch ◽  
Free Dynamic ◽  
Better Than

This paper presents a new bootstrapped switch with high speed and low nonlinear distortion. Instead of fixed voltage, the gate-to-source voltage of switch varies with input to implement first-order body effect compensation. Post-layout simulations have been done in standard 0.18-μm CMOS process at 1.8 V, and results indicate that at 200 MHz sample rate, a peak signal-to-noise-and-distortion ratio (SNDR) of 98.4 dB, spurious-free dynamic range (SFDR) of 105.7 dB and total harmonic distortion (THD) of -104.9 dB can be acquired. For input frequency up to the 60 MHz frequency, proposed structure maintains |THD| over 85 dB, SFDR better than 86 dB, respectively.

scholarly journals Design of a Memristor-Based Digital to Analog Converter (DAC)

Electronics ◽  
2021 ◽  
Vol 10 (5) ◽  
pp. 622
Author(s):  
Ghazal A. Fahmy ◽  
Mohamed Zorkany
Keyword(s):  
Dynamic Range ◽  
Sar Adc ◽  
Large Area ◽  
Digital To Analog Converter ◽  
Analog To Digital ◽  
Low Area ◽  
Switching Power ◽  
Analog Converter ◽  
Low Threshold ◽  
Digital To Analog

A memristor element has been highlighted in recent years and has been applied to several applications. In this work, a memristor-based digital to analog converter (DAC) was proposed due to the fact that a memristor has low area, low power, and a low threshold voltage. The proposed memristor DAC depends on the basic DAC cell, consisting of two memristors connected in opposite directions. This basic DAC cell was used to build and simulate both a 4 bit and an 8 bit DAC. Moreover, a sneak path issue was illustrated and its solution was provided. The proposed design reduced the area by 40%. The 8 bit memristor DAC has been designed and used in a successive approximation register analog to digital converter (SAR-ADC) instead of in a capacitor DAC (which would require a large area and consume more switching power). The SAR-ADC with a memristor-based DAC achieves a signal to noise and distortion ratio (SNDR) of 49.3 dB and a spurious free dynamic range (SFDR) of 61 dB with a power supply of 1.2 V and a consumption of 21 µW. The figure of merit (FoM) of the proposed SAR-ADC is 87.9 fj/Conv.-step. The proposed designs were simulated with optimized parameters using a voltage threshold adaptive memristor (VTEAM) model.

scholarly journals A 28 nm CMOS 10 bit 100 MS/s Asynchronous SAR ADC with Low-Power Switching Procedure and Timing-Protection Scheme

Electronics ◽  
2021 ◽  
Vol 10 (22) ◽  
pp. 2856
Author(s):  
Fang Tang ◽  
Qiyun Ma ◽  
Zhou Shu ◽  
Yuanjin Zheng ◽  
Amine Bermak
Keyword(s):  
Dynamic Range ◽  
Supply Voltage ◽  
Sar Adc ◽  
Cmos Process ◽  
Power Switching ◽  
Analog To Digital ◽  
Protection Scheme ◽  
Area Efficiency ◽  
Asynchronous Sar ◽  
28 Nm

This paper presents a 10 bit 100 MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) without calibration for industrial control system (ICS) applications. Several techniques are adopted in the proposed switching procedure to achieve better linearity, power and area efficiency. A single-side-fixed technique is utilized to reduce the number of capacitors; a parallel split capacitor array in combination with a partially thermometer coded technique can minimize the switching energy, improve speed, and decrease differential non-linearity (DNL). In addition, a compact timing-protection scheme is proposed to ensure the stability of the asynchronous SAR ADC. The proposed ADC is fabricated in a 28 nm CMOS process with an active area of 0.026 mm2. At 100 MS/s, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 51.54 dB and a spurious free dynamic range (SFDR) of 55.12 dB with the Nyquist input. The measured DNL and integral non-linearity (INL) without calibration are +0.37/−0.44 and +0.48/−0.63 LSB, respectively. The power consumption is 1.1 mW with a supply voltage of 0.9 V, leading to a figure of merit (FoM) of 35.6 fJ/conversion-step.

A LOW POWER 13-BIT 50MS/s RECIRCULATING PIPELINE ANALOG TO DIGITAL CONVERTER

2014 ◽  
Vol 23 (06) ◽  
pp. 1450090 ◽  
Author(s):  
ARASH ESMAILI ◽  
HADISEH BABAZADEH ◽  
KHAYROLLAH HADIDI ◽  
ABDOLLAH KHOEI
Keyword(s):  
Power Consumption ◽  
Dynamic Range ◽  
Cmos Technology ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Nyquist Frequency ◽  
Signal To Noise ◽  
Analog To Digital ◽  
Spurious Free Dynamic Range ◽  
Free Dynamic

A 13-bit analog-to-digital converter (ADC) is designed in 0.35 μm CMOS technology that reduces the power consumption through sharing the resources between pipeline stages. Using a dummy sample-and-hold (S/H) and recirculating concept the requirements for the first stage are relaxed and the design restrictions are resolved. This ADC does not use a dedicated S/H and reaches a speed of 50 MS/s. The design is tested with TSMC mixed-signal 0.35 μm technology and post layout simulations shows over 75 dB Signal-to-Noise and Distortion-Ratio (SNDR) and over 85 dB Spurious Free Dynamic Range (SFDR) at the Nyquist frequency. The designed chip occupies an area of 1.3 mm–0.7 mm and consumes 164 mW power at Nyquist from a 3.3 V supply.

Large Spurious-free Dynamic Range RoF Link with Tunable CSR

2021 ◽  
Author(s):  
Ruiqiong Wang ◽  
Yangyu Fan ◽  
Jiajun Tan ◽  
Yongsheng Gao
Keyword(s):  
Dynamic Range ◽  
Spurious Free Dynamic Range ◽  
Free Dynamic
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