Performance Comparison of Lattice-Matched AlInN/GaN/AlGaN/GaN Double-Channel Metal–Oxide–Semiconductor High-Electron Mobility Transistors with Planar Channel and Multiple-Mesa-Fin-Channel Array

In this work, Al0.83In0.17N/GaN/Al0.18Ga0.82N/GaN epitaxial layers used for the fabrication of double-channel metal–oxide–semiconductor high-electron mobility transistors (MOSHEMTs) were grown on silicon substrates using a metalorganic chemical vapor deposition system (MOCVD). A sheet electron density of 1.11 × 1013 cm−2 and an electron mobility of 1770 cm2/V-s were obtained. Using a vapor cooling condensation system to deposit high insulating 30-nm-thick Ga2O3 film as a gate oxide layer, double-hump transconductance behaviors with associated double-hump maximum extrinsic transconductances (gmmax) of 89.8 and 100.1 mS/mm were obtained in the double-channel planar MOSHEMTs. However, the double-channel devices with multiple-mesa-fin-channel array with a gmmax of 148.9 mS/mm exhibited single-hump transconductance behaviors owing to the better gate control capability. Moreover, the extrinsic unit gain cutoff frequency and maximum oscillation frequency of the devices with planar channel and multiple-mesa-fin-channel array were 5.7 GHz and 10.5 GHz, and 6.5 GHz and 12.6 GHz, respectively. Hooge’s coefficients of 7.50 × 10−5 and 6.25 × 10−6 were obtained for the devices with planar channel and multiple-mesa-fin-channel array operating at a frequency of 10 Hz, drain–source voltage of 1 V, and gate–source voltage of 5 V, respectively.

VDS and VGS Depolarization Effect on SiC MOSFET Short-Circuit Withstand Capability Considering Partial Safe Failure-Mode

This paper presents a detailed analysis of 1200 V Silicon Carbide (SiC) power MOSFET exhibiting different short-circuit failure mechanisms and improvement in reliability by VDS and VGS depolarization. The device robustness has undergone an incremental pulse under different density decreasing; either drain-source voltage or gate-driver voltage. Unlike silicon device, the SiC MOSFET failure mechanism firstly displays specific gradual gate-cracks mechanism and progressive gate-damage accumulations greater than 4 µs/9 J·cm−2. Secondly, a classical drain-source thermal runaway appears, as for silicon devices, in a time greater than 9 µs. Correlations with short-circuit energy measurements and temperature simulations are investigated. It is shown that the first mechanism is an incremental soft gate-failure-mode which can be easily used to detect and protect the device by a direct feedback on the gate-driver. Furthermore, it is highlighted that this new mechanism can be sufficiently consolidated to avoid the second drain-source mechanism which is a hard-failure-mode. For this purpose, it is proposed to sufficiently depolarize the on-state gate-drive voltage to reduce the chip heating-rate and thus to decouple the failure modes. The device is much more robust with a short-circuit withstand time higher than 10 µs, as in silicon, no risk of thermal runaway and with an acceptable penalty on RDS-ON.

Design of Low Voltage Quasi-floating Self Cascode Current Mirror

In this paper, a modified structure of self-cascode structure is proposed. In the proposed structure, the MOSFET working in saturation mode is replaced by a Quasi-floating gate MOSFET by which the threshold voltage can be scaled, resulting in an increase in the drain-to-source voltage of other MOSFET operating in the linear region. The increased drain-to-source voltage results in a change in the operating region, which here is from linear to saturation regime. To exploit the performance of the proposed structure, the design of the current mirror circuit is shown in this paper. The proposed architecture when compared with its conventional design showed improvement in performance without affecting the other parameters. The complete design is done using MOSFET models of 180nm technology using Spice at supply dual supply of 0.5V.

A comprehensive analytical model for ambipolar transport in nano-dimensional VOPc/p-6P OHJFET for applications in organic electronics

This paper presents a compact analytical DC model for high mobility VOPc (vanadyl pthalocyanine)/p-6P (para-sexiphenyl) ambipolar organic heterojunction field-effect transistor (OHJFET). The proposed model accounts for both unipolar and ambipolar regimes of VOPc/p-6P ambipolar OHJFET by considering spatial charge carrier density in the channel. The model incorporates subthreshold conduction phenomenon in addition to describing beyond threshold transport. The model is extended to describe ambipolar regime occurring in subthreshold region at low drain to source voltage, VDS. Device characteristics and various parameters obtained are presented and are further used to model recombination zone and channel potential profile. Results obtained, are compared with available experimental data and a good match is observed.

A novel AlGaN/GaN heterostructure field-effect transistor based on open-gate technology

In this study, a novel AlGaN/GaN heterostructure field-effect transistor based on open-gate technology was fabricated. Sample transistors of different structures and sizes were constructed. Through measurements, it was found that by changing the width of the opening, the threshold voltage of the device could be easily modulated across a larger range. The open-gate device had two working modes with different transconductance. When the gate-source voltage VGS ≤ − 4.5 V, only the open region was conductive, and a new working mechanism modulated the channel current. Corresponding theoretical analysis and calculations showed that its saturation mechanism was related to a virtual gate formed by electron injection onto the surface. Also, the gate-source voltage modulated the open channel current by changing the channel electron mobility through polarization Coulomb field scattering. When used as class-A voltage amplifiers, open-gate devices can achieve effective voltage amplification with very low power consumption.

Comparisons on Different Innovative Cascode GaN HEMT E-Mode Power Modules and Their Efficiencies on the Flyback Converter

The conventional cascode structure for driving depletion-mode (D-mode) gallium nitride (GaN) high electron mobility transistors (HEMTs) raises reliability concerns. This is because of the possibility of the gate to source voltage of the GaN HEMT surging to a negative voltage during the turn off transition. The existing solutions for this problem in the literature produce additional drawbacks such as reducing the switching frequency or introducing many additional components. These drawbacks may outweigh the advantages of using a GaN HEMT over its silicon (Si) alternative. This paper proposes two innovative gate drive circuits for D-mode GaN HEMTs—namely the GaN-switching based cascode GaN HEMT and the modified GaN-switching based cascode GaN HEMT. In these schemes, the Si MOSFET in series with the D-mode GaN HEMT is always turned on during regular operation. The GaN HEMT is then switched on and off by using a charge pump based circuit and a conventional gate driver. Since the GaN HEMT is driven independently, the highly negative gate-to-source voltage surge during turn off is avoided, and in addition, high switching frequency operation is made possible. Only two diodes and one capacitor are used in each of the schemes. The application of the proposed circuits is experimentally demonstrated in a high voltage flyback converter, where more than 96% efficiency is obtained for 60 W output load.

Nonlinearity Analysis of Quantum Capacitance and its Effect on Nano-Graphene Field Effect Transistor characteristics

A simple, compact, and fundamental physics-based quasi-analytic model for Single layer graphene field effect transistors (GFETs) with large area graphene is presented in which the quantum mechanical density gradient method is utilised. The basic device physics of the two-dimensional (2D) graphene channel is studied analytically. This modeling leads to the precise drain current calculation of the GFETs. The drain current calculation for GFETs starts from charge carrier concentration, its density of states and quantum capacitance(QC). QC depends on the channel voltage as a function of gate to source voltage Vgs and drain to source voltage Vds primarily. The formulation of the drain current with velocity saturation has been done by the Monte Carlo simulation method. The performance of the analytical GFETs model is present the precise values of QC, its impact on drain current and transfer as well as output characteristics. The impact of QC at nanometer technology adds the nonlinearity to characteristics curves. The proposed method provides better results as compared with the previous analytical and simulated results.