New Hardware Architecture for Self-Organizing Map Used for Color Vector Quantization

2019 ◽  
Vol 29 (01) ◽  
pp. 2050002
Author(s):  
Khaled Ben Khalifa ◽  
Ahmed Ghazi Blaiech ◽  
Mehdi Abadi ◽  
Mohamed Hedi Bedoui

In this paper, we present a new generic architectural approach of a Self-Organizing Map (SOM). The proposed architecture, called the Diagonal-SOM (D-SOM), is described as an Hardware–Description-Language as an intellectual property kernel with easily adjustable parameters.The D-SOM architecture is based on a generic formalism that exploits two levels of the nested parallelism of neurons and connections. This solution is therefore considered as a system based on the cooperation of a distributed set of independent computations. The organization and structure of these calculations process an oriented data flow in order to find a better treatment distribution between different neuroprocessors. To validate the D-SOM architecture, we evaluate the performance of several SOM network architectures after their integration on a Xilinx Virtex-7 Field Programmable Gate Array support. The proposed solution allows the easy adaptation of learning to a large number of SOM topologies without any considerable design effort. [Formula: see text] SOM hardware is validated through FPGA implementation, where temporal performance is almost twice as fast as that obtained in the recent literature. The suggested D-SOM architecture is also validated through simulation on variable-sized SOM networks applied to color vector quantization.

2019 ◽  
Vol 2019 ◽  
pp. 1-14 ◽  
Author(s):  
Khaled Ben Khalifa ◽  
Ahmed Ghazi Blaiech ◽  
Mohamed Hédi Bedoui

In this article, we propose to design a new modular architecture for a self-organizing map (SOM) neural network. The proposed approach, called systolic-SOM (SSOM), is based on the use of a generic model inspired by a systolic movement. This model is formed by two levels of nested parallelism of neurons and connections. Thus, this solution provides a distributed set of independent computations between the processing units called neuroprocessors (NPs) which define the SSOM architecture. The NP modules have an innovative architecture compared to those proposed in the literature. Indeed, each NP performs three different tasks without requiring additional external modules. To validate our approach, we evaluate the performance of several SOM network architectures after their integration on an FPGA support. This architecture has achieved a performance almost twice as fast as that obtained in the recent literature.


2014 ◽  
pp. 27-33
Author(s):  
Mounir Bouhedda ◽  
Mokhtar Attari

The aim of this paper is to introduce a new architecture using Artificial Neural Networks (ANN) in designing a 6-bit nonlinear Analog to Digital Converter (ADC). A study was conducted to synthesise an optimal ANN in view to FPGA (Field Programmable Gate Array) implementation using Very High-speed Integrated Circuit Hardware Description Language (VHDL). Simulation and tests results are carried out to show the efficiency of the designed ANN.


Author(s):  
Melody Y. Kiang ◽  
Dorothy M. Fisher ◽  
Michael Y. Hu ◽  
Robert T. Chi

This chapter presents an extended Self-Organizing Map (SOM) network and demonstrates how it can be used to forecast market segment membership. The Kohonen’s SOM network is an unsupervised learning neural network that maps n-dimensional input data to a lower dimensional (usually one- or two-dimensional) output map while maintaining the original topological relations. We apply an extended version of SOM networks that further groups the nodes on the output map into a user-specified number of clusters to a residential market data set from AT&T. Specifically, the extended SOM is used to group survey respondents using their attitudes towards modes of communication. We then compare the extended SOM network solutions with a two-step procedure that uses the factor scores from factor analysis as inputs to K-means cluster analysis. Results using AT&T data indicate that the extended SOM network performs better than the two-step procedure.


Author(s):  
B Murali Krishna ◽  
◽  
B.T. Krishna ◽  
K Babulu ◽  
◽  
...  

A comparison of linear and quadratic transform implementation on field programmable gate array (FPGA) is presented. Popular linear transform namely Stockwell Transform and Smoothed Pseudo Wigner Ville Distribution (SPWVD) transform from Quadratic transforms is considered for the implementation on FPGA. Both the transforms are coded in Verilog hardware description language (Verilog HDL). Complex calculations of transformation are performed by using CORDIC algorithm. From FPGA family, Spartan-6 is chosen as hardware device to implement. Synthetic chirp signal is taken as input to test the both designed transforms. Summary of hardware resource utilization on Spartan-6 for both the transforms is presented. Finally, it is observed that both the transforms S-Transform and SPWVD are computed with low elapsed time with respect to MATLAB simulation.


2021 ◽  
Vol 13 (0) ◽  
pp. 1-5
Author(s):  
Kęstutis Bartnykas

Field-programmable logic arrays are often used in courses on computer architecture. The student must describe the processor with the external components necessary for its operation in the specified HDL (hardware description language) language according to the provided specification during a certain number of projects. The weakness of this approach is that the basis of such projects is a processor of one specific architecture, so the lecturer faces the issue of individualization of projects. This article proposes a solution based on dedicated processors instead of one programmable processor of a specific architecture. It’s shown here that the issue of project individualization is easier solvable in the proposed way, and it does not deviate from the theory of computer architecture, because the programmable processor is a generalization of a dedicated processor. The article describes project design ideas based on dedicated processors and gives some examples. Represented different instance than was applied during practical sessions of Computer Architecture that are held at the Department of Electronic Systems within VILNIUS TECH, i.e. certain modifications, and additions were applied.


2022 ◽  
Vol 12 (2) ◽  
pp. 655
Author(s):  
Baligh Naji ◽  
Chokri Abdelmoula ◽  
Mohamed Masmoudi

This paper presents the design and development of a technique for an Autonomous and Versatile mode Parking System (AVPS) that combines a various number of parking modes. The proposed approach is different from that of many developed parking systems. Previous research has focused on choosing only a parking lot starting from two parking modes (which are parallel and perpendicular). This research aims at developing a parking system that automatically chooses a parking lot starting from four parking modes. The automatic AVPS was proposed for the car-parking control problem, and could be potentially exploited for future vehicle generation. A specific mode can be easily computed using the proposed strategy. A variety of candidate modes could be generated using one developed real time VHDL (VHSIC Hardware Description Language) algorithm providing optimal solutions with performance measures. Based on simulation and experimental results, the AVPS is able to find and recognize in advance which parking mode to select. This combination describes full implementation on a mobile robot, such as a car, based on a specific FPGA (Field-Programmable Gate Array) card. To prove the effectiveness of the proposed innovation, an evaluation process comparing the proposed technique with existing techniques was conducted and outlined.


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