A method for synthesis and optimization for linear nearest neighbor quantum circuits by parallel processing

2018 ◽  
Vol 18 (13&14) ◽  
pp. 1095-1114
Author(s):  
Zongyuan Zhang ◽  
Zhijin Guan ◽  
Hong Zhang ◽  
Haiying Ma ◽  
Weiping Ding
Keyword(s):  
Parallel Processing ◽  
Large Scale ◽  
Nearest Neighbor ◽  
Matrix Multiplication ◽  
Quantum Circuit ◽  
Quantum Circuits ◽  
Quantum Cost ◽  
The Matrix ◽  
Speed Up ◽  
Serial Algorithm

In order to realize the linear nearest neighbor{(LNN)} of the quantum circuits and reduce the quantum cost of linear reversible quantum circuits, a method for synthesizing and optimizing linear reversible quantum circuits based on matrix multiplication of the structure of the quantum circuit is proposed. This method shows the matrix representation of linear quantum circuits by multiplying matrices of different parts of the whole circuit. The LNN realization by adding the SWAP gates is proposed and the equivalence of two ways of adding the SWAP gates is proved. The elimination rules of the SWAP gates between two overlapped adjacent quantum gates in different cases are proposed, which reduce the quantum cost of quantum circuits after realizing the LNN architecture. We propose an algorithm based on parallel processing in order to effectively reduce the time consumption for large-scale quantum circuits. Experiments show that the quantum cost can be improved by 34.31\% on average and the speed-up ratio of the GPU-based algorithm can reach 4 times compared with the CPU-based algorithm. The average time optimization ratio of the benchmark large-scale circuits in RevLib processed by the parallel algorithm is {95.57\%} comparing with the serial algorithm.

scholarly journals Connectivity matrix model of quantum circuits and its application to distributed quantum circuit optimization

2021 ◽  
Vol 20 (7) ◽  
Author(s):  
Ismail Ghodsollahee ◽  
Zohreh Davarzani ◽  
Mariam Zomorodi ◽  
Paweł Pławiak ◽  
Monireh Houshmand ◽  
...  
Keyword(s):  
Quantum Computation ◽  
Quantum Computer ◽  
Quantum Circuit ◽  
Quantum Circuits ◽  
Connectivity Matrix ◽  
Circuit Optimization ◽  
Novel Approach ◽  
The Matrix ◽  
Minimum Number ◽  
Two Phases

AbstractAs quantum computation grows, the number of qubits involved in a given quantum computer increases. But due to the physical limitations in the number of qubits of a single quantum device, the computation should be performed in a distributed system. In this paper, a new model of quantum computation based on the matrix representation of quantum circuits is proposed. Then, using this model, we propose a novel approach for reducing the number of teleportations in a distributed quantum circuit. The proposed method consists of two phases: the pre-processing phase and the optimization phase. In the pre-processing phase, it considers the bi-partitioning of quantum circuits by Non-Dominated Sorting Genetic Algorithm (NSGA-III) to minimize the number of global gates and to distribute the quantum circuit into two balanced parts with equal number of qubits and minimum number of global gates. In the optimization phase, two heuristics named Heuristic I and Heuristic II are proposed to optimize the number of teleportations according to the partitioning obtained from the pre-processing phase. Finally, the proposed approach is evaluated on many benchmark quantum circuits. The results of these evaluations show an average of 22.16% improvement in the teleportation cost of the proposed approach compared to the existing works in the literature.

An FPGA-based quantum circuit emulation framework using heisenberg representation

2018 ◽  
Vol 16 (06) ◽  
pp. 1850052
Author(s):  
Y. H. Lee ◽  
M. Khalil-Hani ◽  
M. N. Marsono
Keyword(s):  
Large Scale ◽  
Scale Up ◽  
Quantum Circuit ◽  
Theoretical Research ◽  
Resource Requirement ◽  
Heisenberg Representation ◽  
Speed Up ◽  
Computing Platforms ◽  
Classical Computing

While physical realization of practical large-scale quantum computers is still ongoing, theoretical research of quantum computing applications is facilitated on classical computing platforms through simulation and emulation methods. Nevertheless, the exponential increase in resource requirement with the increase in the number of qubits is an inherent issue in classical modeling of quantum systems. In the effort to alleviate the critical scalability issue in existing FPGA emulation works, a novel FPGA-based quantum circuit emulation framework based on Heisenberg representation is proposed in this paper. Unlike previous works that are restricted to the emulations of quantum circuits of small qubit sizes, the proposed FPGA emulation framework can scale-up to 120-qubit on Altera Stratix IV FPGA for the stabilizer circuit case study while providing notable speed-up over the equivalent simulation model.

scholarly journals An Innovative Genetic Algorithm for the Quantum Circuit Compilation Problem

2019 ◽  
Vol 33 ◽  
pp. 7707-7714
Author(s):  
Riccardo Rasconi ◽  
Angelo Oddi
Keyword(s):  
Genetic Algorithm ◽  
Nearest Neighbor ◽  
Quantum Algorithms ◽  
Quantum Circuit ◽  
Quantum Circuits ◽  
Heuristic Function ◽  
Circuit Realization ◽  
Benchmark Instances ◽  
Technological Limitations ◽  
Selection Of

Quantum Computing represents the next big step towards speed boost in computation, which promises major breakthroughs in several disciplines including Artificial Intelligence. This paper investigates the performance of a genetic algorithm to optimize the realization (compilation) of nearest-neighbor compliant quantum circuits. Currrent technological limitations (e.g., decoherence effect) impose that the overall duration (makespan) of the quantum circuit realization be minimized, and therefore the makespanminimization problem of compiling quantum algorithms on present or future quantum machines is dragging increasing attention in the AI community. In our genetic algorithm, a solution is built utilizing a novel chromosome encoding where each gene controls the iterative selection of a quantum gate to be inserted in the solution, over a lexicographic double-key ranking returned by a heuristic function recently published in the literature.Our algorithm has been tested on a set of quantum circuit benchmark instances of increasing sizes available from the recent literature. We demonstrate that our genetic approach obtains very encouraging results that outperform the solutions obtained in previous research against the same benchmark, succeeding in significantly improving the makespan values for a great number of instances.

scholarly journals Qulacs: a fast and versatile quantum circuit simulator for research purpose

Quantum ◽  
2021 ◽  
Vol 5 ◽  
pp. 559
Author(s):  
Yasunari Suzuki ◽  
Yoshiaki Kawase ◽  
Yuya Masumura ◽  
Yuria Hiraga ◽  
Masahiro Nakadai ◽  
...  
Keyword(s):  
Fault Tolerant ◽  
Quantum Algorithm ◽  
Quantum Circuit ◽  
Quantum Circuits ◽  
Research Purpose ◽  
Numerical Techniques ◽  
Circuit Simulator ◽  
Speed Up ◽  
Near Term

To explore the possibilities of a near-term intermediate-scale quantum algorithm and long-term fault-tolerant quantum computing, a fast and versatile quantum circuit simulator is needed. Here, we introduce Qulacs, a fast simulator for quantum circuits intended for research purpose. We show the main concepts of Qulacs, explain how to use its features via examples, describe numerical techniques to speed-up simulation, and demonstrate its performance with numerical benchmarks.

scholarly journals Synthesis of quantum circuits in Linear Nearest neighbor Model using Positive Davio Lattices

2011 ◽  
Vol 24 (1) ◽  
pp. 71-87 ◽  
Author(s):  
Marek Perkowski ◽  
Martin Lukac ◽  
Dipal Shah ◽  
Michitaka Kameyama
Keyword(s):  
Nearest Neighbor ◽  
Dimensional Space ◽  
Synthesis Method ◽  
Logic Synthesis ◽  
Quantum Circuits ◽  
Quantum Gates ◽  
Synthesis Methods ◽  
Cost Models ◽  
Quantum Cost ◽  
One Dimensional

We present a logic synthesis method based on lattices that realize quantum arrays in One-Dimensional Ion Trap technology. This means that all gates are built from 2x2 quantum primitives that are located only on neighbor qubits in a one-dimensional space (called also vector of qubits or Linear Nearest Neighbor (LNN) architecture). The Logic circuits designed by the proposed method are realized only with 3*3 Toffoli, Feynman and NOT quantum gates and the usage of the commonly used multi-input Toffoli gates is avoided. This realization method of quantum circuits is different from most of reversible circuits synthesis methods from the literature that use only high level quantum cost based on the number of quantum gates. Our synthesis approach applies to both standard and LNN quantum cost models. It leads to entirely new CAD algorithms for circuit synthesis and substantially decreases the quantum cost for LNN quantum circuits. The drawback of synthesizing circuits in the presented LNN architecture is the addition of ancilla qubits.

Analyzing Heuristic-based Randomized Search Strategies for the Quantum Circuit Compilation Problem

2020 ◽  
Vol 174 (3-4) ◽  
pp. 259-281
Author(s):  
Angelo Oddi ◽  
Riccardo Rasconi
Keyword(s):  
Quantum Computing ◽  
Nearest Neighbor ◽  
Quantum Algorithm ◽  
Quantum Circuit ◽  
Quantum Circuits ◽  
Quantum Gates ◽  
Ranking Functions ◽  
Solution Quality ◽  
Circuit Realization ◽  
Definition Of

In this work we investigate the performance of greedy randomised search (GRS) techniques to the problem of compiling quantum circuits to emerging quantum hardware. Quantum computing (QC) represents the next big step towards power consumption minimisation and CPU speed boost in the future of computing machines. Quantum computing uses quantum gates that manipulate multi-valued bits (qubits). A quantum circuit is composed of a number of qubits and a series of quantum gates that operate on those qubits, and whose execution realises a specific quantum algorithm. Current quantum computing technologies limit the qubit interaction distance allowing the execution of gates between adjacent qubits only. This has opened the way to the exploration of possible techniques aimed at guaranteeing nearest-neighbor (NN) compliance in any quantum circuit through the addition of a number of so-called swap gates between adjacent qubits. In addition, technological limitations (decoherence effect) impose that the overall duration (makespan) of the quantum circuit realization be minimized. One core contribution of the paper is the definition of two lexicographic ranking functions for quantum gate selection, using two keys: one key acts as a global closure metric to minimise the solution makespan; the second one is a local metric, which favours the mutual approach of the closest qstates pairs. We present a GRS procedure that synthesises NN-compliant quantum circuits realizations, starting from a set of benchmark instances of different size belonging to the Quantum Approximate Optimization Algorithm (QAOA) class tailored for the MaxCut problem. We propose a comparison between the presented meta-heuristics and the approaches used in the recent literature against the same benchmarks, both from the CPU efficiency and from the solution quality standpoint. In particular, we compare our approach against a reference benchmark initially proposed and subsequently expanded in [1] by considering: (i) variable qubit state initialisation and (ii) crosstalk constraints that further restrict parallel gate execution.

Linear Nearest Neighbor Realization of Quantum Circuits Using Clustering and Look-ahead Policy

2020 ◽  
Vol 29 (16) ◽  
pp. 2050263
Author(s):  
Anirban Bhattacharjee ◽  
Chandan Bandyopadhyay ◽  
Bappaditya Mondal ◽  
Hafizur Rahaman
Keyword(s):  
Nearest Neighbor ◽  
Quantum Circuit ◽  
Quantum Circuits ◽  
Physical Realization ◽  
Emerging Trends ◽  
Look Ahead ◽  
Wide Range ◽  
Clustering Approach ◽  
On Chip ◽  
The Impact

In the last couple of years, quantum computing has come out as emerging trends of computation not only due to its immense popularity but also for its commitment towards physical realization of quantum circuit in on-chip units. At the same time, the process of physical realization has faced several design constraints and one such problem is nearest neighbor (NN) enforcement which demands all the operating qubits to be placed adjacent in the implementable circuit. Though SWAP gate embedment can transform a design into NN architecture, it still creates overhead in the design. So, designing algorithms to restrict the use of SWAPs bears high importance. Considering this fact, in this work, we are proposing a heuristic-based improved qubit placement strategy for efficient implementation of NN circuit. Two different design policies are being developed here. In the first scheme, a global reordering technique based on clustering approach is shown. In the second scheme, a local reordering technique based on look-ahead policy is developed. This look-ahead strategy considers the impact over the gates in the circuit and thereby estimates the effect using a cost metric to decide the suitable option for SWAP implementation. Furthermore, the joint use of both the ordering schemes also has been explored here. To ascertain the correctness of our design algorithms, we have tested them over a wide range of benchmarks and the obtained results are compared with some state-of-the-art design approaches. From this comparison, we have witnessed a considerable reduction on SWAP cost in our design scheme against the reported works’ results.

scholarly journals HHL Analysis and Simulation Verification Based on Origin Quantum Platform

2021 ◽  
Vol 2113 (1) ◽  
pp. 012083
Author(s):  
Xiaonan Liu ◽  
Lina Jing ◽  
Lin Han ◽  
Jie Gao
Keyword(s):  
Large Scale ◽  
Weather Forecasting ◽  
Sparse Matrix ◽  
Linear Equations ◽  
Quantum Algorithm ◽  
Equation System ◽  
Quantum Circuit ◽  
Small Scale ◽  
The Matrix ◽  
Time Required

Abstract Solving large-scale linear equations is of great significance in many engineering fields, such as weather forecasting and bioengineering. The classical computer solves the linear equations, no matter adopting the elimination method or Kramer’s rule, the time required for solving is in a polynomial relationship with the scale of the equation system. With the advent of the era of big data, the integration of transistors is getting higher and higher. When the size of transistors is close to the order of electron diameter, quantum tunneling will occur, and Moore’s Law will not be followed. Therefore, the traditional computing model will not be able to meet the demand. In this paper, through an in-depth study of the classic HHL algorithm, a small-scale quantum circuit model is proposed to solve a 2×2 linear equations, and the circuit diagram and programming are used to simulate and verify on the Origin Quantum Platform. The fidelity under different parameter values reaches more than 90%. For the case where the matrix to be solved is a sparse matrix, the quantum algorithm has an exponential speed improvement over the best known classical algorithm.

Energy Cost of Quantum Circuit Optimisation: Predicting That Optimising Shor’s Algorithm Circuit Uses 1 GWh

2022 ◽  
Vol 3 (1) ◽  
pp. 1-14
Author(s):  
Alexandru Paler ◽  
Robert Basmadjian
Keyword(s):  
Programming Languages ◽  
Energy Cost ◽  
Large Scale ◽  
State Of The Art ◽  
Quantum Circuit ◽  
Quantum Circuits ◽  
Bucket Brigade ◽  
Depth Study ◽  
Cost Metrics ◽  
Optimisation Methods

Quantum circuits are difficult to simulate, and their automated optimisation is complex as well. Significant optimisations have been achieved manually (pen and paper) and not by software. This is the first in-depth study on the cost of compiling and optimising large-scale quantum circuits with state-of-the-art quantum software. We propose a hierarchy of cost metrics covering the quantum software stack and use energy as the long-term cost of operating hardware. We are going to quantify optimisation costs by estimating the energy consumed by a CPU doing the quantum circuit optimisation. We use QUANTIFY, a tool based on Google Cirq, to optimise bucket brigade QRAM and multiplication circuits having between 32 and 8,192 qubits. Although our classical optimisation methods have polynomial complexity, we observe that their energy cost grows extremely fast with the number of qubits. We profile the methods and software and provide evidence that there are high constant costs associated to the operations performed during optimisation. The costs are the result of dynamically typed programming languages and the generic data structures used in the background. We conclude that state-of-the-art quantum software frameworks have to massively improve their scalability to be practical for large circuits.

An efficient conversion of quantum circuits to a linear nearest neighbor architecture

2011 ◽  
Vol 11 (1&2) ◽  
pp. 142-166
Author(s):  
Yuichi Hirata ◽  
Masaki Nakanishi ◽  
Shigeru Yamashita ◽  
Yasuhiko Nakashima
Keyword(s):  
Quantum Computation ◽  
Time Complexity ◽  
Nearest Neighbor ◽  
Quantum Circuit ◽  
Quantum Circuits ◽  
Quantum Bits ◽  
Efficient Conversion ◽  
Conversion Method ◽  
Additional Circuitry

Several promising implementations of quantum computation rely on a Linear Nearest Neighbor (LNN) architecture, which arranges quantum bits on a line, and allows neighbor interactions only. Therefore, several specific circuits have been designed on an LNN architecture. However, a general and efficient conversion method for an arbitrary circuit has not been established. Therefore, this paper gives an efficient conversion technique to convert quantum circuits to an LNN architecture. When a quantum circuit is converted to an LNN architecture, the objective is to reduce the size of the additional circuit added by the conversion and the time complexity of the conversion. The proposed method requires less additional circuitry and time complexity compared with naive techniques. To develop the method, we introduce two key theorems that may be interesting on their own. In addition, the proposed method also achieves less overhead than some known circuits designed from scratch on an LNN architecture.

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