Architecture-Level Optimization on Digital Silicon Photomultipliers for Medical Imaging

Silicon photomultipliers (SiPMs) are arrays of single-photon avalanche diodes (SPADs) connected in parallel. Analog silicon photomultipliers are built in custom technologies optimized for detection efficiency. Digital silicon photomultipliers are built in CMOS technology. Although CMOS SPADs are less sensitive, they can incorporate additional functionality at the sensor plane, which is required in some applications for an accurate detection in terms of energy, timestamp, and spatial location. This additional circuitry comprises active quenching and recharge circuits, pulse combining and counting logic, and a time-to-digital converter. This, together with the disconnection of defective SPADs, results in a reduction of the light-sensitive area. In addition, the pile-up of pulses, in space and in time, translates into additional efficiency losses that are inherent to digital SiPMs. The design of digital SiPMs must include some sort of optimization of the pixel architecture in order to maximize sensitivity. In this paper, we identify the most relevant variables that determine the influence of SPAD yield, fill factor loss, and spatial and temporal pile-up in the photon detection efficiency. An optimum of 8% is found for different pixel sizes. The potential benefits of molecular imaging of these optimized and small-sized pixels with independent timestamping capabilities are also analyzed.

ASIC Implementation of Linear Equalizer Using Adaptive FIR Filter

Power consumption plays a crucial role in the design of portable wireless communication devices, as it has a direct influence on the battery weight and volume required for operation. This article presents a novel design for a linear LMS equalizer for the optimization of filter order. The article describes the use of a variable length algorithm for dynamically updating the tap-length of the LMS adaptive filter to optimize the performance and for reducing the power in the adaptive filter core. An algorithm is applied to reduce and adjust the order of the filter in linear equalizer according to the channel conditions. The proposed design is implemented in the synopsis TSMC 65nm technology. The results from using the algorithm uses 28% less power when compared with the conventional 64-tap fixed length adaptive filter design. It has also been shown that the low-complexity of the additional circuitry needed for the variable length adaptive filter presents minimal overhead for this architecture.

ESTATE: A Lightweight and Low Energy Authenticated Encryption Mode

NIST has recently initiated a standardization project for efficient lightweight authenticated encryption schemes. SUNDAE, a candidate in this project, achieves optimal state size which results in low circuit overhead on top of the underlying block cipher. In addition, SUNDAE provides security in nonce-misuse scenario as well. However, in addition to the block cipher circuit, SUNDAE also requires some additional circuitry for multiplication by a primitive element. Further, it requires an additional block cipher invocation to create the starting state. In this paper, we propose a new lightweight and low energy authenticated encryption family, called ESTATE, that significantly improves the design of SUNDAE in terms of implementation costs (both hardware area and energy) and efficient processing of short messages. In particular, ESTATE does not require an additional multiplication circuit, and it reduces the number of block cipher calls by one. Moreover, it provides integrity security even under the release of unverified plaintext (or RUP) model. ESTATE is based on short-tweak tweakable block ciphers (or tBC, small ’t’ denotes short tweaks) and we instantiate it with two recently designed tBCs: TweAES and TweGIFT. We also propose a low latency variant of ESTATE, called sESTATE, that uses a round-reduced (6 rounds) variant of TweAES called TweAES-6. We provide comprehensive FPGA based hardware implementation for all the three instances. The implementation results depict that ESTATE_TweGIFT-128 (681 LUTs, 263 slices) consumes much lesser area as compared to SUNDAE_GIFT-128 (931 LUTs, 310 slices). When we moved to the AES variants, along with the area-efficiency (ESTATE_TweAES consumes 1901 LUTs, 602 slices while SUNDAE_AES-128 needs 1922 LUTs, 614 slices), we also achieve higher throughput for short messages (For 16-byte message, a throughput of 1251.10 and 945.36 Mbps for ESTATE_TweAES and SUNDAE_AES-128 respectively).

MODERN IMPLEMENTATION OF JOHNSON COUNTER IN LOW POWER DIGITAL LOGICS USING CLOCK TIMING TECHNIQUES

The instinctive purpose of this study is to make VLSI circuits as low power consuming as possible. A lot of work has been done to reduce the operational power dissipation of the circuit, and reducing the power of sequential circuits is most important as it has clock as one of its input. Johnson counters are the sequential circuits which have so many unwanted switching of the clock pulses. Clock gating is the technique which reduces the power dissipation by eliminating the unwanted switching of the clock pulses. In this technique, the clock is supplied when output is different from the input and the clock is suppressed when output is same as the input. A new design of Johnson counter was studied in which additional circuitry of clock gating was used the unnecessary switching of the clock pulses and thus, to improve the power dissipation. It reduced the power to appreciable amount but this logic increased the chip area increasing the number of transistors. In this design, the optimization can be done in various blocks. Flip-flop being used in master slave mode consume huge power and the logic gates are also the site of power dissipation. So, a new design is proposed which comprises of proposed flip-flop design and modified logic gates design and a proposed design is simulated with the help of HSPICE which gives huge power reduction.

A Hybrid Topological Design of Led Driver for Automotive Applications

Light-emitting diodes (LEDs) have long been utilized as the default component for signaling and interior lighting applications in automotive industry. The response rate of an LED as compared to a traditional incandescent bulb is ten times faster. The ease of maintenance and controllability feature of LEDs also makes them a natural choice for intelligent lighting system. This lighting can be adjusted based on the sensor inputs of a vehicle with ease. The multi lighting capabilities of a LED driver provides options that can address multiple applications with the same LEDs. A constant current is required for uniform LED lighting. Owing to the high reliability on LEDs for an array of applications in the automotive sector, additional circuitry for over voltage protection, under voltage protection, reverse polarity risk, over current protection, over temperature protection and short circuit protection needs to incorporated. The proposed design provides a improvement of 5% over the state of the art existing topology for over voltage protection.

Hardware Approach to Mitigate the Effects of Module Mismatch in a Grid-connected Photovoltaic System: A Review

This study reviews the hardware approach to mitigate the effects of module mismatch in a grid-connected photovoltaic (PV) system. Unlike software solutions, i.e. the maximum power tracking algorithm, hardware techniques are well suited to enhance energy yield because of their inherent ability to extract energy from the mismatched module. Despite the extra cost of the additional circuitry, hardware techniques have recently gained popularity because of their long-term financial benefits. Notwithstanding the growing interest in this topic, review papers that provide updates on the technological developments of the three main hardware solutions, namely micro inverter, DC power optimizer, and energy recovery circuits, are lacking. This is in contrast to software solutions, which have had a considerable number of reputable reviews. Thus, a comprehensive review paper is appropriate at this juncture to provide up-to-date information on the latest topologies, highlight their merits/drawbacks, and evaluate their comparative performance.

A CMOS Self-Bias CTAT Current Generator with Improved Supply Sensitivity

The role of complimentary to absolute temperature (CTAT) circuit in current mode bandgap has been described. Loop-gain problems with the existing self-bias MOS-based CTAT generator were discussed. A simple modification to the existing circuit was proposed to enhance the loop-gain by [Formula: see text]20[Formula: see text]dB without adding additional circuitry leading to zero additional power consumption. Power Supply Rejection and sensitivity to [Formula: see text] will be improved due to the higher loop-gain. A prototype has been developed to demonstrate the proposal robustness across PVT corners. Simulation results show 20.5[Formula: see text]dB PSRR improvement and 7.5% improvement in sensitivity to [Formula: see text]. The proposed solution consumes 180[Formula: see text]nW power from 1[Formula: see text]V power supply voltage and occupies 3300[Formula: see text][Formula: see text]m2 silicon area.

Low Cost Instrumentation for Electrical Impedance Tomography in Biomedical Applications

This poster reports the design, implementation and testing of a portable and inexpensive bio-impedance measurement system intended for electrical impedance tomography (EIT) in cell cultures. The system is based on the AD5933 impedance analyser integrated circuit with additional circuitry to enable four-terminal measurement. Initial results of impedance measurements are reported along with an EIT image reconstructed using the open source EIDORS package.

Design and implementation of Butler matrix-based beam-forming networks for low sidelobe level electronically scanned arrays

In this work, the design, fabrication, and testing of low sidelobe level (SLL) Butler matrix-based beamformers is presented. The paper is divided in two parts. The first part deals with the conventional technique of simultaneous excitation of input ports. The second part introduces some novel modified low SLL Butler matrices, as an alternative advantageous design choice. Circuit architecture makes use of asymmetric branch line couplers able to provide high values of output power division ratios. Radiation patterns with SLLs far lower than −23 dB are achieved, without the use of any additional circuitry, in opposition to the case of simultaneous port excitation. Apart from SLL reduction, the switched line-phase shifter technique is applied in order to increase the number of radiated beams and improve scanning coverage. The beamformers are suitable for interference suppressing point-to-multipoint ground communications, satellite and radar/EW/SIGINT systems. Several microstrip circuit prototypes are designed, fabricated, and tested, whereas extended simulation and measurements results are adduced.

Associative learning is necessary but not sufficient for mirror neuron development

Existing computational models of the mirror system demonstrate the additional circuitry needed for mirror neurons to display the range of properties that they exhibit. Such models emphasize the need for existing connectivity to form visuomotor associations, processing to reduce the space of possible inputs, and demonstrate the role neurons with mirror properties might play in monitoring one's own actions.