A Low Supply Voltage, Low Line Sensitivity, and High PSRR Subthreshold CMOS Voltage Reference

Author(s):  
Arvind Thakur ◽  
Rishikesh Pandey ◽  
Shireesh Kumar Rai
2017 ◽  
Vol 64 (12) ◽  
pp. 3036-3046 ◽  
Author(s):  
Arthur Campos de Oliveira ◽  
David Cordova ◽  
Hamilton Klimach ◽  
Sergio Bampi

Electronics ◽  
2019 ◽  
Vol 8 (11) ◽  
pp. 1271
Author(s):  
Brito ◽  
Colombo ◽  
Moreno ◽  
El-Sankary

This work presents an investigation of the temperature behavior of self-cascode composite transistors (SCCTs). Results supported by silicon measurements show that SCCTs can be used to generate a proportional to absolute temperature voltage or even a temperature-compensated voltage. Based on the achieved results, a new circuit topology of a resistorless voltage reference circuit using a Schottky diode is also presented. The circuit was fabricated in a 130 nm BiCMOS process and occupied a silicon area of 67.98 µm × 161.7 µm. The averaged value of the output voltage is 720.4 mV, and its averaged line regulation performance is 2.3 mV/V, calculated through 26 characterized chip samples. The averaged temperature coefficient (TC) obtained through five chip samples is 56 ppm/°C in a temperature range from −40 to 85°C. A trimming circuit is also included in the circuit topology to mitigate the impact of the fabrication process effects on its TC. The circuit operates with a supply voltage range from 1.1 to 2.5 V.


2020 ◽  
Vol 1 ◽  
pp. 100-106
Author(s):  
Jie Lin ◽  
Lidan Wang ◽  
Yan Lu ◽  
Chenchang Zhan

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