NOVEL EMBEDDED CODING TECHNIQUE USING ARRAY CODES AND STATISTICAL CHANNEL EVALUATION

1999 ◽  
Vol 09 (05n06) ◽  
pp. 307-319 ◽  
Author(s):  
K. M. S. SOYJAUDAH ◽  
M. I. JAHMEERBACUS
Keyword(s):  
Maximum Likelihood ◽  
Error Correction ◽  
Error Detection ◽  
Code Rate ◽  
Evaluation Technique ◽  
Maximum Likelihood Decoding ◽  
Embedded Coding ◽  
Outer Code ◽  
Array Codes

Previously, the proposed embedded coding techniques based on the row and column array codes, employ a combination of inner codes for error correction and outer codes for error detection. The outer codes involve the addition of further redundant bits. This reduces the overall code rate and hence, the throughput of the system. Furthermore, the decoding of these array codes is not a maximum likelihood decoding. In this paper, we propose a novel embedded coding technique that employs a combination of row and column array codes as well as the generalized array codes, but no outer code. The decoding of these codes is a maximum likelihood decoding and the error detection is done by a new statistical channel evaluation technique that uses the trellises of the component codes embedded in the main block.

Maximum likelihood decoding of RLL-FEC array codes on partial response channels

1993 ◽  
Vol 29 (16) ◽  
pp. 1406 ◽  
Author(s):  
G.S. Markarian ◽  
M. Naderi ◽  
B. Honary ◽  
A. Popplewell ◽  
J.J. O'Reilly
Keyword(s):  
Maximum Likelihood ◽  
Partial Response ◽  
Maximum Likelihood Decoding ◽  
Partial Response Channels ◽  
Array Codes

Maximum-likelihood decoding of array codes with trellis structure

1993 ◽  
Vol 140 (5) ◽  
pp. 340 ◽  
Author(s):  
B. Honary ◽  
L. Kaya ◽  
G.S. Markarian ◽  
M. Darnell
Keyword(s):  
Maximum Likelihood ◽  
Maximum Likelihood Decoding ◽  
Array Codes

scholarly journals Artificial Neural Network Assisted Error Correction for MLC NAND Flash Memory

Micromachines ◽  
2021 ◽  
Vol 12 (8) ◽  
pp. 879
Author(s):  
Ruiquan He ◽  
Haihua Hu ◽  
Chunru Xiong ◽  
Guojun Han
Keyword(s):  
Neural Network ◽  
Error Correction ◽  
Error Detection ◽  
Flash Memory ◽  
Nand Flash ◽  
Data Reliability ◽  
Nand Flash Memory ◽  
Process Technology ◽  
Noise Mitigation ◽  
Memory Channel

The multilevel per cell technology and continued scaling down process technology significantly improves the storage density of NAND flash memory but also brings about a challenge in that data reliability degrades due to the serious noise. To ensure the data reliability, many noise mitigation technologies have been proposed. However, they only mitigate one of the noises of the NAND flash memory channel. In this paper, we consider all the main noises and present a novel neural network-assisted error correction (ANNAEC) scheme to increase the reliability of multi-level cell (MLC) NAND flash memory. To avoid using retention time as an input parameter of the neural network, we propose a relative log-likelihood ratio (LLR) to estimate the actual LLR. Then, we transform the bit detection into a clustering problem and propose to employ a neural network to learn the error characteristics of the NAND flash memory channel. Therefore, the trained neural network has optimized performances of bit error detection. Simulation results show that our proposed scheme can significantly improve the performance of the bit error detection and increase the endurance of NAND flash memory.

scholarly journals Exponential suppression of bit or phase errors with cyclic error correction

Nature ◽  
2021 ◽  
Vol 595 (7867) ◽  
pp. 383-387
Author(s):  
◽  
Zijun Chen ◽  
Kevin J. Satzinger ◽  
Juan Atalaya ◽  
Alexander N. Korotkov ◽  
...  
Keyword(s):  
Error Correction ◽  
Error Detection ◽  
Fault Tolerant ◽  
Error Rates ◽  
Quantum Error Correction ◽  
Superconducting Qubits ◽  
Two Dimensional ◽  
Logical Error ◽  
Quantum Error ◽  
Logical Qubit

AbstractRealizing the potential of quantum computing requires sufficiently low logical error rates1. Many applications call for error rates as low as 10−15 (refs. 2–9), but state-of-the-art quantum platforms typically have physical error rates near 10−3 (refs. 10–14). Quantum error correction15–17 promises to bridge this divide by distributing quantum logical information across many physical qubits in such a way that errors can be detected and corrected. Errors on the encoded logical qubit state can be exponentially suppressed as the number of physical qubits grows, provided that the physical error rates are below a certain threshold and stable over the course of a computation. Here we implement one-dimensional repetition codes embedded in a two-dimensional grid of superconducting qubits that demonstrate exponential suppression of bit-flip or phase-flip errors, reducing logical error per round more than 100-fold when increasing the number of qubits from 5 to 21. Crucially, this error suppression is stable over 50 rounds of error correction. We also introduce a method for analysing error correlations with high precision, allowing us to characterize error locality while performing quantum error correction. Finally, we perform error detection with a small logical qubit using the 2D surface code on the same device18,19 and show that the results from both one- and two-dimensional codes agree with numerical simulations that use a simple depolarizing error model. These experimental demonstrations provide a foundation for building a scalable fault-tolerant quantum computer with superconducting qubits.

Sign in / Sign up

Export Citation Format

Share Document