High-Speed Low-Power Ring Oscillator Using Inverted-Structure Modulation-Doped GaAs/n-AlGaAs Field-Effect Transistors

1985 ◽  
Vol 24 (Part 1, No. 8) ◽  
pp. 1061-1064 ◽  
Author(s):  
Haruhisa Kinoshita ◽  
Seiji Nishi ◽  
Masahiro Akiyama ◽  
Katsuzo Kaminishi
Keyword(s):  
Low Power ◽  
Field Effect ◽  
High Speed ◽  
Field Effect Transistors ◽  
Ring Oscillator ◽  
Inverted Structure ◽  
Structure Modulation

Effects of dual-spacer dielectrics on low-power and high-speed performance of sub-10 nm tunneling field-effect transistors

2016 ◽  
Vol 55 (6S1) ◽  
pp. 06GG02 ◽  
Author(s):  
Young Jun Yoon ◽  
Jae Hwa Seo ◽  
Seongjae Cho ◽  
Hyuck-In Kwon ◽  
Jung-Hee Lee ◽  
...  
Keyword(s):  
Low Power ◽  
Field Effect ◽  
High Speed ◽  
Field Effect Transistors ◽  
Tunneling Field Effect Transistors ◽  
Speed Performance

scholarly journals Implementation of 20 nm Graphene Channel Field Effect Transistors Using Silvaco TCAD Tool to Improve Short Channel Effects over Conventional MOSFETs

2021 ◽  
Vol 7 (1) ◽  
pp. 18-29
Author(s):  
Vinod Pralhad Tayade ◽  
Swapnil Laxman Lahudkar
Keyword(s):  
Low Power ◽  
Field Effect ◽  
High Speed ◽  
Field Effect Transistors ◽  
Oxide Semiconductor ◽  
Short Channel Effects ◽  
Short Channel ◽  
Channel Effects ◽  
20 Nm ◽  
Graphene Material

In recent years, demands for high speed and low power circuits have been raised. As conventional metal oxide semiconductor field effect transistors (MOSFETs) are unable to satisfy the demands due to short channel effects, the purpose of the study is to design an alternative of MOSFETs. Graphene FETs are one of the alternatives of MOSFETs due to the excellent properties of graphene material. In this work, a user-defined graphene material is defined, and a graphene channel FET is implemented using the Silvaco technology computer-aided design (TCAD) tool at 100 nm and scaled to 20 nm channel length. A silicon channel MOSFET is also implemented to compare the performance. The results show the improvement in subthreshold slope (SS) = 114 mV/dec, ION/IOFF ratio = 14379, and drain induced barrier lowering (DIBL) = 123 mV/V. It is concluded that graphene FETs are suitable candidates for low power applications.

Performance of Inverted Structure Modulation Doped Schottky Barrier Field Effect Transistors

1982 ◽  
Vol 21 (Part 2, No. 4) ◽  
pp. L223-L224 ◽  
Author(s):  
R. E. Thorne ◽  
R. Fischer ◽  
S. L. Su ◽  
W. Kopp ◽  
T. J. Drummond ◽  
...  
Keyword(s):  
Schottky Barrier ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Inverted Structure ◽  
Structure Modulation

Li Intercalation Effects on Interface Resistances of High‐Speed and Low‐Power WSe 2 Field‐Effect Transistors

2020 ◽  
Vol 30 (45) ◽  
pp. 2003688
Author(s):  
Yong Seon Shin ◽  
Kiyoung Lee ◽  
Dinh Loc Duong ◽  
Jun Seok Kim ◽  
Won Tae Kang ◽  
...  
Keyword(s):  
Low Power ◽  
Field Effect ◽  
High Speed ◽  
Field Effect Transistors
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