Flip-Chip Bonding Using Superconducting Solder Bump

1995 ◽  
Vol 34 (Part 1, No. 8A) ◽  
pp. 4043-4046 ◽  
Author(s):  
Toshinori Ogashiwa ◽  
Hiroshi Nakagawa ◽  
HideyukiAkimoto ◽  
Hiroyuki Shigyo ◽  
Susumu Takada
2003 ◽  
Vol 150 (10) ◽  
pp. C730 ◽  
Author(s):  
Susumu Arai ◽  
Hideki Akatsuka ◽  
Norio Kaneko

2002 ◽  
Vol 43 (6) ◽  
pp. 1336-1340 ◽  
Author(s):  
Soon-Min Hong ◽  
Choon-Sik Kang ◽  
Jae-Pil Jung

1983 ◽  
Vol 54 (9) ◽  
pp. 5282-5286 ◽  
Author(s):  
Jiro Temmyo ◽  
Katsuhiko Aoki ◽  
Haruo Yoshikiyo ◽  
Shigeyuki Tsurumi ◽  
Yoshiaki Takeuchi

2007 ◽  
Vol 30 (1) ◽  
pp. 27-33 ◽  
Author(s):  
Kun-Mo Chu ◽  
Won-Kyoung Choi ◽  
Young-Chul Ko ◽  
Jin-Ho Lee ◽  
Hyo-Hoon Park ◽  
...  

Author(s):  
George F. Gaut

Abstract Access to the solder bump and under-fill material of flip-chip devices has presented a new problem for failure analysts. The under-fill and solder bumps have also added a new source for failure causes. A new tool has become available that can reduce the time required to analyze this area of a flip-chip package. By using precision selective area milling it is possible to remove material (die or PCB) that will allow other tools to expose the source of the failure.


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