Studies on Chemical Methods to Expose Gate/Tunnel Oxide and Identification of Gate/Tunnel Oxide Defects in Wafer Fabrication

In failure analysis of wafer fabrication, currently, three different types of chemical methods including 6:6:1 (Acetic Acid/HNO3/HF), NaOH and Choline are used in removing polysilicon (poly) layer and exposing the gate/tunnel oxide underneath. However, usage is limited due to their disadvantages. For example, 6:6:1 is a relatively fast etchant, but it is difficult to control the etch time and keep the oxide layer intact. Also, while using NaOH to remove poly and expose the silicon oxide, the solution needs to be heated. It is also difficult to etch a poly layer with a WSix or a CoSix silicide using NaOH. In this paper, we will discuss these 3 etchants in terms of their advantages and disadvantages. We will then introduce a new poly etchant, called HB91. HB91 is useful for removing poly to expose the gate/tunnel oxide for identification of related defects. HB91 is actually a mixture of two chemicals namely nitric acid (HNO3) and buffer oxide etchant (BOE) in a 9:1 ratio. The experimental results show that it is highly selective in poly removal with respect to the gate/tunnel oxide and is a suitable poly etchant especially for removing polysilicon with/without WSix and CoSix in the large capacitor structure. Application results of this poly etchant (HB91) will be presented.

Methodology for TEM Analysis of Barrier Profiles

Device shrinkage has resulted in thinner barriers and smaller vias. Transmission Electron Microscopy (TEM) has become a common technique for barrier profile analysis because of its high image resolution. TEM sample preparation and image interpretation becomes difficult when the size of the small cylindrical via is close to the TEM sample thickness. Effects of different sample thickness and specimen preparation methods, therefore, have been investigated. An automatic FIB program has been shown to be useful in via sample preparation. Techniques for imaging a TEM specimen will be discussed in the paper. Conventional TEM bright field (BF) image is adequate to examine the barrieronly via; however, other techniques are more suitable for a Cu filled via.

The Use of Precision Selective Area Milling for Failure Analysis of Flip-Chip Packages

Access to the solder bump and under-fill material of flip-chip devices has presented a new problem for failure analysts. The under-fill and solder bumps have also added a new source for failure causes. A new tool has become available that can reduce the time required to analyze this area of a flip-chip package. By using precision selective area milling it is possible to remove material (die or PCB) that will allow other tools to expose the source of the failure.

Circuit Voltage Probe Based on Time-Integrated Measurements of Optical Emission From Leakage Current

Hot-carrier luminescence emission is used to diagnose the cause of excess quiescence current, IDDQ, in a low power circuit implemented in CMOS 7SF technology. We found by optical inspection of the chip that the high IDDQ is related to the low threshold, Vt, device process and in particular to transistors with minimum channel length (0.18 μm). In this paper we will also show that it is possible to gain knowledge regarding the operating conditions of the IC from the analysis of optical emission due to leakage current, aside from simply locating defects and failures. In particular, we will show how it is possible to calculate the voltage drop across the circuit power grid from time-integrated acquisitions of leakage luminescence.

Prospects of Time-Resolved Photon Emission as a Debug Tool

Dynamic hot-electron emission using time-resolved photon counting can address the long-term failure analysis and debug requirements of the semiconductor industry's advanced devices. This article identifies the detector performance parameters and components that are required to scale and keep pace with the industry's requirements. It addresses the scalability of dynamic emission with the semiconductor advanced device roadmap. It is important to understand the limitations to determining that a switching event has occurred. The article explains the criteria for event detection, which is suitable for tracking signal propagation and looking for logic or other faults in which timing is not critical. It discusses conditions for event timing, whose goal is to determine accurately when a switching event has occurred, usually for speed path analysis. One of the uses of a dynamic emission system is to identify faults by studying the emission as a general function of time.

Methodology to Correlate Defect Reduction Systems to Electrical Test Data via Artificially Manufactured Defects

This paper describes a methodology for correlating physical defect inspection/navigation systems with electrical bitmap data through the fabrication of artificial defects via reticle alterations or circuit modifications using an inline FIB. The methodology chosen consisted of altering decommissioned reticles to create defects resulting in both open and shorted circuits within areas of an AMD microprocessor cache. The reticles were subsequently scanned using a KLA SL300HR StarLight inspection system to confirm their location, while wafers processed on these reticles were scanned at several layers using standard inline metrology. Finally, the wafers were electrically tested, bitmapped, and physically deprocessed. All defect data was then analyzed and cross-correlated between each system, uncovering some important system deficiencies and learning opportunities. Data and images are included to support the significance and effectiveness of such a methodology.

Thin-Die Flip Chip Physical-FA Process Flow

The use of flip chip technology inside component packaging, so called flip chip in package (FCIP), is an increasingly common package type in the semiconductor industry because of high pin-counts, performance and reliability. Sample preparation methods and flows which enable physical failure analysis (PFA) of FCIP are thus in demand to characterize defects in die with these package types. As interconnect metallization schemes become more dense and complex, access to the backside silicon of a functional device also becomes important for fault isolation test purposes. To address these requirements, a detailed PFA flow is described which chronicles the sample preparation methods necessary to isolate a physical defect in the die of an organic-substrate FCIP.

Evaluation of Package Defects by Thermal Imaging Techniques

Study presented here has shown that Infrared thermography has the potential to be a nondestructive analysis tool for evaluating package sublayer defects. Thermal imaging is achieved by applying pulsed external heating to the package surface and monitoring the surface thermal response as a function of time with a high-speed IR camera. Since the thermal response of the surface is affected by the defects such as voids and delamination below the package surface, the technique can be used to assist package defects detection and analysis.

A Working Method for Adapting the (SEM) Scanning Electron Microscope to Produce (STEM) Scanning Transmission Electron Microscope Images

This paper describes the problems encountered and solutions found to the practical objective of developing an imaging technique that would produce a more detailed analysis of IC material structures then a scanning electron microscope. To find a solution to this objective the theoretical idea of converting a standard SEM to produce a STEM image was developed. This solution would enable high magnification, material contrasting, detailed cross sectional analysis of integrated circuits with an ordinary SEM. This would provide a practical and cost effective alternative to Transmission Electron Microscopy (TEM), where the higher TEM accelerating voltages would ultimately yield a more detailed cross sectional image. An additional advantage, developed subsequent to STEM imaging was the use of EDX analysis to perform high-resolution element identification of IC cross sections. High-resolution element identification when used in conjunction with high-resolution STEM images provides an analysis technique that exceeds the capabilities of conventional SEM imaging.

Fault Localization and Functional Testing of ICs by Lock-in Thermography

In this paper new thermographic techniques with significant improved temperature and/or spatial resolution are presented and compared with existing techniques. In infrared (IR) lock-in thermography heat sources in an electronic device are periodically activated electrically, and the surface is imaged by a free-running IR camera. By computer processing and averaging the images over a certain acquisition time, a surface temperature modulation below 100 µK can be resolved. Moreover, the effective spatial resolution is considerably improved compared to stead-state thermal imaging techniques, since the lateral heat diffusion is suppressed in this a.c. technique. However, a serious limitation is that the spatial resolution is limited to about 5 microns due to the IR wavelength range of 3 -5 µm used by the IR camera. Nevertheless, we demonstrate that lock-in thermography reliably allows the detection of defects in ICs if their power exceeds some 10 µW. The imaging can be performed also through the silicon substrate from the backside of the chip. Also the well-known fluorescent microthermal imaging (FMI) technique can be be used in lock-in mode, leading to a temperature resolution in the mK range, but a spatial resolution below 1 micron.