Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction

2005 ◽  
Author(s):  
Yan Lin ◽  
Fei Li ◽  
Lei He
Keyword(s):  
Power Reduction ◽  
Power Gating ◽  
Fine Grained ◽  
Interconnect Power

An integrated DFT solution for power reduction in scan test applications by low power gating scan cell

Integration ◽  
2017 ◽  
Vol 57 ◽  
pp. 108-124 ◽  
Author(s):  
Mahshid Mojtabavi Naeini ◽  
Sreedharan Baskara Dass ◽  
Chia Yee Ooi ◽  
Tomokazu Yoneda ◽  
Michiko Inoue
Keyword(s):  
Low Power ◽  
Power Reduction ◽  
Power Gating ◽  
Scan Test

scholarly journals Fine-Grained FSMD Power Gating Considering Power Overhead

ETRI Journal ◽  
2011 ◽  
Vol 33 (3) ◽  
pp. 466-469 ◽  
Author(s):  
Chi-Hoon Shin
Keyword(s):  
Power Gating ◽  
Fine Grained

scholarly journals An Efficient Power Optimized 32 bit BCD Adder Using Multi-Channel Technique

2017 ◽  
Vol 6 (02) ◽  
pp. 07-12
Author(s):  
Diksha Siddhamshittiwar
Keyword(s):  
Average Power ◽  
Full Adder ◽  
Deep Submicron ◽  
Power Reduction ◽  
Vlsi Circuits ◽  
Power Gating ◽  
Static Power ◽  
Simulation Results ◽  
Efficient Power ◽  
Standby Mode

Static power reduction is a challenge in deep submicron VLSI circuits. In this paper 28T full adder circuit, 14T full adder circuit and 32 bit power gated BCD adder using the full adders respectively were designed and their average power was compared. In existing work a conventional full adder is designed using 28T and the same is used to design 32 bit BCD adder. In the proposed architecture 14T transmission gate based power gated full adder is used for the design of 32 bit BCD adder. The leakage supremacy dissipated during standby mode in all deep submicron CMOS devices is reduced using efficient power gating and multi-channel technique. Simulation results were obtained using Tanner EDA and TSMC_180nm library file is used for the design of 28T full adder, 14T full adder and power gated BCD adder and a significant power reduction is achieved in the proposed architecture.

Aggressive Fine-Grained Power Gating of NoC Buffers

2020 ◽  
Vol 39 (11) ◽  
pp. 3177-3189
Author(s):  
Yibo Wu ◽  
Leibo Liu ◽  
Liang Wang ◽  
Xiaohang Wang ◽  
Jie Han ◽  
...  
Keyword(s):  
Power Gating ◽  
Fine Grained
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