Leakage power reduction of an SRAM-based look-up table (LUT) in field-programmable gate array (FPGA) has been achieved in this work by implementing an efficient and dynamic power gating technique. The logic of gating is based on the theory of automatically shutting down the power supply to the inactive blocks of LUT during runtime, contrary to all previous works which involved manual intervention for the implementation of power gating. Two techniques of power gating are introduced in this work, PG1 and PG2. PG1 results in more power savings than PG2, however, PG2 has an advantage of low area overhead. Simulation has been carried out for all possible input combinations of LUT, designed in Cadence Virtuoso tool at 45[Formula: see text]nm technology. The results indicate a leakage power reduction of up to 50% in PG1 technique, with an average area overhead of 14.15%. The power savings in PG2 is up to 38%, with a minimal increase in area of 1.76%. The power bounce noise is also analyzed for the proposed techniques and reported.
Leakage power reduction for coarse grained dynamically reconfigurable processor arrays with fine grained Power Gating technique
