A methodology to improve yield in analog circuits by using geometric programming

2010 ◽  
Author(s):  
Jorge Johanny Sáenz Noval ◽  
Elkim Felipe Roa Fuentes ◽  
Armando Ayala Pabón ◽  
Wilhelmus Van Noije
Keyword(s):  
Analog Circuits ◽  
Geometric Programming

Design Optimizaion of Gm-C Filters via Geometric Programming

2017 ◽  
Vol E100.C (4) ◽  
pp. 407-415
Author(s):  
Minyoung YOON ◽  
Byungjoon KIM ◽  
Jintae KIM ◽  
Sangwook NAM
Keyword(s):  
Geometric Programming

Synthesis of Network Functions for the Discrete-Analog Circuits with Switched Capacitors

2017 ◽  
pp. 47-53
Author(s):  
Konstantin Sergeyevich GORSHKOV ◽  
◽  
Sergei Aleksandrovich KURGANOV ◽  
Vladimir Valentinovich FILARETOV ◽  
◽  
...  
Keyword(s):  
Analog Circuits ◽  
Discrete Analog ◽  
Switched Capacitors ◽  
Network Functions

Analog Circuit Failure Analysis Using Time-Resolved Emission

2005 ◽  
Author(s):  
B.J. Cain ◽  
G.L. Woods ◽  
A. Syed ◽  
R. Herlein ◽  
Toshihiro Nomura
Keyword(s):  
Analog Circuits ◽  
Integrated Circuit ◽  
Analog Circuit ◽  
Photon Emission ◽  
Nonlinear Process ◽  
Time Resolved ◽  
Non Invasive ◽  
Highly Nonlinear ◽  
Excellent Spatial Resolution ◽  
5 Ghz

Abstract Time-Resolved Emission (TRE) is a popular technique for non-invasive acquisition of time-domain waveforms from active nodes through the backside of an integrated circuit. [1] State-of-the art TRE systems offer high bandwidths (> 5 GHz), excellent spatial resolution (0.25um), and complete visibility of all nodes on the chip. TRE waveforms are typically used for detecting incorrect signal levels, race conditions, and/or timing faults with resolution of a few ps. However, extracting the exact voltage behavior from a TRE waveform is usually difficult because dynamic photon emission is a highly nonlinear process. This has limited the perceived utility of TRE in diagnosing analog circuits. In this paper, we demonstrate extraction of voltage waveforms in passing and failing conditions from a small-swing, differential logic circuit. The voltage waveforms obtained were crucial in corroborating a theory for some failures inside an 0.18um ASIC.

Laser Based Analysis on Analog Circuits with Feedback Loops and a Case Study

2006 ◽  
Author(s):  
Fubin Zhang ◽  
David Maxwell
Keyword(s):  
Success Rate ◽  
High Resistance ◽  
Analog Circuits ◽  
Analog Circuit ◽  
Feedback Loops ◽  
Induced Voltage ◽  
Analog Device ◽  
Analog Ic ◽  
Successful Isolation

Abstract Based on the understanding of laser based techniques’ physics theory and the topology/structure of analog circuit systems with feedback loops, the propagation of laser induced voltage/current alteration inside the analog IC is evaluated. A setup connection scheme is proposed to monitor this voltage/current alteration to achieve a better success rate in finding the fail site or defect. Finally, a case of successful isolation of a high resistance via on an analog device is presented.

Concepts for In Situ Diagnostics in Analog Microelectronic Circuits

2007 ◽  
Author(s):  
Ted Kolasa ◽  
Alfredo Mendoza
Keyword(s):  
Analog Circuits ◽  
System Architecture ◽  
Analog Circuit ◽  
Fault Localization ◽  
Diagnostic System ◽  
Diagnostic Capability ◽  
Common Signal ◽  
Diagnostic Capabilities ◽  
In Situ Diagnostics

Abstract Comprehensive in situ (designed-in) diagnostic capabilities have been incorporated into digital microelectronic systems for years, yet similar capabilities are not commonly incorporated into the design of analog microelectronics. And as feature sizes shrink and back end interconnect metallization becomes more complex, the need for effective diagnostics for analog circuits becomes ever more critical. This paper presents concepts for incorporating in situ diagnostic capability into analog circuit designs. Aspects of analog diagnostic system architecture are discussed as well as nodal measurement scenarios for common signal types. As microelectronic feature sizes continue to shrink, diagnostic capabilities such as those presented here will become essential to the process of fault localization in analog circuits.

scholarly journals 1/f Noise Modelling and Characterization for CMOS Quanta Image Sensors

Sensors ◽  
2019 ◽  
Vol 19 (24) ◽  
pp. 5459
Author(s):  
Wei Deng ◽  
Eric R. Fossum
Keyword(s):  
Analog Circuits ◽  
Image Sensor ◽  
Image Sensors ◽  
Correlated Double Sampling ◽  
Cmos Image Sensors ◽  
Source Follower ◽  
Cmos Analog Circuits ◽  
Different Origins ◽  
Noise Models ◽  
Fitting Model

This work fits the measured in-pixel source-follower noise in a CMOS Quanta Image Sensor (QIS) prototype chip using physics-based 1/f noise models, rather than the widely-used fitting model for analog designers. This paper discusses the different origins of 1/f noise in QIS devices and includes correlated double sampling (CDS). The modelling results based on the Hooge mobility fluctuation, which uses one adjustable parameter, match the experimental measurements, including the variation in noise from room temperature to –70 °C. This work provides useful information for the implementation of QIS in scientific applications and suggests that even lower read noise is attainable by further cooling and may be applicable to other CMOS analog circuits and CMOS image sensors.

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