Parallel-Pipelined Video Processing in Multicore Heterogeneous Systems on Chip

2021 ◽  
Vol 26 (2) ◽  
pp. 172-183
Author(s):  
E.S. Yanakova ◽  
◽  
G.T. Macharadze ◽  
L.G. Gagarina ◽  
A.A. Shvachko ◽  
...  
Keyword(s):  
Video Processing ◽  
High Efficiency ◽  
Heterogeneous Systems ◽  
Video Data ◽  
System Level ◽  
Video Information ◽  
Systems On Chip ◽  
The Face ◽  
Parallel Pipelined ◽  
On Chip

A turn from homogeneous to heterogeneous architectures permits to achieve the advantages of the efficiency, size, weight and power consumption, which is especially important for the built-in solutions. However, the development of the parallel software for heterogeneous computer systems is rather complex task due to the requirements of high efficiency, easy programming and the process of scaling. In the paper the efficiency of parallel-pipelined processing of video information in multiprocessor heterogeneous systems on a chip (SoC) such as DSP, GPU, ISP, VDP, VPU and others, has been investigated. A typical scheme of parallel-pipelined processing of video data using various accelerators has been presented. The scheme of the parallel-pipelined video data on heterogeneous SoC 1892VM248 has been developed. The methods of efficient parallel-pipelined processing of video data in heterogeneous computers (SoC), consisting of the operating system level, programming technologies level and the application level, have been proposed. A comparative analysis of the most common programming technologies, such as OpenCL, OpenMP, MPI, OpenAMP, has been performed. The analysis has shown that depend-ing on the device finite purpose two programming paradigms should be applied: based on OpenCL technology (for built-in system) and MPI technology (for inter-cell and inter processor interaction). The results obtained of the parallel-pipelined processing within the framework of the face recognition have confirmed the effectiveness of the chosen solutions.

Systemc and OCAPI-XL Based System-Level Design for Reconfigurable Systems-on-Chip

2006 ◽  
pp. 255-269 ◽  
Author(s):  
Kari Tiensyrjä ◽  
Miroslav Cupak ◽  
Kostas Masselos ◽  
Marko Pettissalo ◽  
Konstantinos Potamianos ◽  
...  
Keyword(s):  
System Level ◽  
Reconfigurable Systems ◽  
System Level Design ◽  
Systems On Chip ◽  
Level Design ◽  
On Chip

scholarly journals A novel chaotic system based on coupled map lattice and its application in HEVC encryption

2021 ◽  
Vol 18 (6) ◽  
pp. 9410-9429
Author(s):  
Qing Ye ◽  
◽  
Qiaojia Zhang ◽  
Sijie Liu ◽  
Kaiqiang Chen ◽  
...  
Keyword(s):  
Chaotic System ◽  
Stream Cipher ◽  
High Efficiency ◽  
Chaotic Map ◽  
Large Data ◽  
Coupled Map Lattice ◽  
Video Data ◽  
Video Encryption ◽  
High Efficiency Video Coding ◽  
Video Information

<abstract> <p>Video information is currently widely used in various fields. Compared with image and text data, video data has the characteristics of large data volume, strong data relevance, and large data redundancy, which makes traditional cryptographic systems no longer suitable for video encryption systems. The paper proposes a new chaotic system based on coupled map lattice (CML) and applies it to high efficiency video coding (HEVC) video encryption. The chaotic system logistic-iterative chaotic map with infinite collapses-coupled map lattice (L-ICMIC-CML), which is improved on the basis of the ICMIC system and combined with CML, generates stream ciphers and encrypts some syntax elements of HEVC. The experimental results show that the stream cipher generated by the L-ICMIC-CML system passes the SP800-22 Revla test and has strong randomness. Applying the stream cipher to the proposed HEVC encryption scheme, through the analysis of the encryption scheme's security, encryption time and encryption efficiency, it is better than other chaotic system encryption schemes. The video encryption system proposed in this paper is both safe and efficient.</p> </abstract>

Stereo vision architecture for heterogeneous systems-on-chip

2018 ◽  
Vol 17 (2) ◽  
pp. 393-415 ◽  
Author(s):  
Stefania Perri ◽  
Fabio Frustaci ◽  
Fanny Spagnolo ◽  
Pasquale Corsonello
Keyword(s):  
Stereo Vision ◽  
Heterogeneous Systems ◽  
Systems On Chip ◽  
On Chip

System-Level Design of NoC-Based Dependable Embedded Systems

2014 ◽  
pp. 478-512
Author(s):  
Mihkel Tagel ◽  
Peeter Ellervee ◽  
Gert Jervan
Keyword(s):  
Design Space Exploration ◽  
System Level ◽  
System Level Design ◽  
Levels Of Abstraction ◽  
Technology Scaling ◽  
Communication Problems ◽  
Systems On Chip ◽  
Level Design ◽  
On Chip ◽  
Manufacturing Yield

Technology scaling into subnanometer range will have impact on the manufacturing yield and quality. At the same time, complexity and communication requirements of systems-on-chip (SoC) are increasing, thus making a SoC designer goal to design a fault-free system a very difficult task. Network-on-chip (NoC) has been proposed as one of the alternatives to solve some of the on-chip communication problems and to address dependability at various levels of abstraction. This chapter concentrates on system-level design issues of NoC-based systems. It describes various methods proposed for NoC architecture analysis and optimization, and gives an overview of different system-level fault tolerance methods. Finally, the chapter presents a system-level design framework for performing design space exploration for dependable NoC-based systems.

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