scholarly journals A Non-Intrusive Tool Chain to Optimize MPSoC End-to-End Systems

2021 ◽  
Vol 18 (2) ◽  
pp. 1-22
Author(s):  
Maxime France-Pillois ◽  
Jérôme Martin ◽  
Frédéric Rousseau
Keyword(s):  
Multiprocessor System ◽  
Accurate Information ◽  
Tool Chain ◽  
Fine Grain ◽  
End To End ◽  
On Chip ◽  
Offline Processing ◽  
Time Required ◽  
Software Execution ◽  
Behavioral Information

Multi-core systems are now found in many electronic devices. But does current software design fully leverage their capabilities? The complexity of the hardware and software stacks in these platforms requires software optimization with end-to-end knowledge of the system. To optimize software performance, we must have accurate information about system behavior and time losses. Standard monitoring engines impose tradeoffs on profiling tools, making it impossible to reconcile all the expected requirements: accurate hardware views, fine-grain measurements, speed, and so on. Subsequently, new approaches have to be examined. In this article, we propose a non-intrusive, accurate tool chain, which can reveal and quantify slowdowns in low-level software mechanisms. Based on emulation, this tool chain extracts behavioral information (time, contention) through hardware side channels, without distorting the software execution flow. This tool consists of two parts. (1) An online acquisition part that dumps hardware platform signals. (2) An offline processing part that consolidates meaningful behavioral information from the dumped data. Using our tool chain, we studied and propose optimizations to MultiProcessor System on Chip (MPSoC) support in the Linux kernel, saving about 60% of the time required for the release phase of the GNU OpenMP synchronization barrier when running on a 64-core MPSoC.

A high performance scalable fuzzy based modified Asymmetric Heterogene Multiprocessor System on Chip (AHt-MPSOC) reconfigurable architecture

2021 ◽  
pp. 1-12
Author(s):  
Arun Prasath Raveendran ◽  
Jafar A. Alzubi ◽  
Ramesh Sekaran ◽  
Manikandan Ramachandran
Keyword(s):  
High Performance ◽  
Standard Technique ◽  
System On Chip ◽  
Mixed Integer ◽  
Multiprocessor System ◽  
Compound System ◽  
Available Bandwidth ◽  
Mip Model ◽  
Fpga Chip ◽  
On Chip

This Ensuing generation of FPGA circuit tolerates the combination of lot of hard and soft cores as well as devoted accelerators on a chip. The Heterogene Multi-Processor System-on-Chip (Ht-MPSoC) architecture accomplishes the requirement of modern applications. A compound System on Chip (SoC) system designed for single FPGA chip, and that considered for the performance/power consumption ratio. In the existing method, a FPGA based Mixed Integer Programming (MIP) model used to define the Ht-MPSoC configuration by taking into consideration the sharing hardware accelerator between the cores. However, here, the sharing method differs from one processor to another based on FPGA architecture. Hence, high number of hardware resources on a single FPGA chip with low latency and power targeted. For this reason, a fuzzy based MIP and Graph theory based Traffic Estimator (GTE) are proposed system used to define New asymmetric multiprocessor heterogene framework on microprocessor (AHt-MPSoC) architecture. The bandwidths, energy consumption, wait and transmission range are better accomplished in this suggested technique than the standard technique and it is also implemented with a multi-task framework. The new Fuzzy control-based AHt-MPSoC analysis proves significant improvement of 14.7 percent in available bandwidth and 89.8 percent of energy minimized to various traffic scenarios as compared to conventional method.

scholarly journals A Stochastic Model to Describe the Scattering in the Response of Polysilicon MEMS

2021 ◽  
Vol 2 (1) ◽  
pp. 95
Author(s):  
Luca Dassi ◽  
Marco Merola ◽  
Eleonora Riva ◽  
Angelo Santalucia ◽  
Andrea Venturelli ◽  
...  
Keyword(s):  
Silicon Film ◽  
Micro Fabrication ◽  
Micro Electro Mechanical Systems ◽  
Local Fluctuations ◽  
Stochastic Framework ◽  
On Line ◽  
Chip Testing ◽  
On Chip ◽  
Time Required ◽  
Polycrystalline Silicon Film

The current miniaturization trend in the market of inertial microsystems is leading to movable device parts with sizes comparable to the characteristic length-scale of the polycrystalline silicon film morphology. The relevant output of micro electro-mechanical systems (MEMS) is thus more and more affected by a scattering, induced by features resulting from the micro-fabrication process. We recently proposed an on-chip testing device, specifically designed to enhance the aforementioned scattering in compliance with fabrication constraints. We proved that the experimentally measured scattering cannot be described by allowing only for the morphology-affected mechanical properties of the silicon films, and etch defects must be properly accounted for too. In this work, we discuss a fully stochastic framework allowing for the local fluctuations of the stiffness and of the etch-affected geometry of the silicon film. The provided semi-analytical solution is shown to catch efficiently the measured scattering in the C-V plots collected through the test structure. This approach opens up the possibility to learn on-line specific features of the devices, and to reduce the time required for their calibration.

scholarly journals Operating System for Runtime Reconfigurable Multiprocessor Systems

2011 ◽  
Vol 2011 ◽  
pp. 1-16 ◽  
Author(s):  
Diana Göhringer ◽  
Michael Hübner ◽  
Etienne Nguepi Zeutebouo ◽  
Jürgen Becker
Keyword(s):  
Operating System ◽  
Resource Management ◽  
Multiprocessor System ◽  
Task Mapping ◽  
Access Port ◽  
Novel Approach ◽  
Hardware Resource ◽  
Hardware Architectures ◽  
On Chip ◽  
Internal Configuration

Operating systems traditionally handle the task scheduling of one or more application instances on processor-like hardware architectures. RAMPSoC, a novel runtime adaptive multiprocessor System-on-Chip, exploits the dynamic reconfiguration on FPGAs to generate, start and terminate hardware and software tasks. The hardware tasks have to be transferred to the reconfigurable hardware via a configuration access port. The software tasks can be loaded into the local memory of the respective IP core either via the configuration access port or via the on-chip communication infrastructure (e.g. a Network-on-Chip). Recent-series of Xilinx FPGAs, such as Virtex-5, provide two Internal Configuration Access Ports, which cannot be accessed simultaneously. To prevent conflicts, the access to these ports as well as the hardware resource management needs to be controlled, e.g. by a special-purpose operating system running on an embedded processor. For that purpose and to handle the relations between temporally and spatially scheduled operations, the novel approach of an operating system is of high importance. This special purpose operating system, called CAP-OS (Configuration Access Port-Operating System), which will be presented in this paper, supports the clients using the configuration port with the services of priority-based access scheduling, hardware task mapping and resource management.

scholarly journals Memory Map: A Multiprocessor Cache Simulator

2012 ◽  
Vol 2012 ◽  
pp. 1-12 ◽  
Author(s):  
Shaily Mittal ◽  
Nitin
Keyword(s):  
Shared Memory ◽  
Data Flow ◽  
Memory Systems ◽  
System On Chip ◽  
Multiprocessor System ◽  
Flow Management ◽  
Hit Rate ◽  
Multiple Processors ◽  
On Chip ◽  
Cache Miss

Nowadays, Multiprocessor System-on-Chip (MPSoC) architectures are mainly focused on by manufacturers to provide increased concurrency, instead of increased clock speed, for embedded systems. However, managing concurrency is a tough task. Hence, one major issue is to synchronize concurrent accesses to shared memory. An important characteristic of any system design process is memory configuration and data flow management. Although, it is very important to select a correct memory configuration, it might be equally imperative to choreograph the data flow between various levels of memory in an optimal manner. Memory map is a multiprocessor simulator to choreograph data flow in individual caches of multiple processors and shared memory systems. This simulator allows user to specify cache reconfigurations and number of processors within the application program and evaluates cache miss and hit rate for each configuration phase taking into account reconfiguration costs. The code is open source and in java.

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