Testing for clonal hematopoiesis of indeterminate potential in breast cancer survivors.

e24108 Background: Clonal hematopoiesis of Indeterminate Potential (CHIP) is associated with adverse clinical outcomes including increased risk of hematologic malignancies and heart disease. Limited data suggest an increased prevalence of CHIP in patients treated for solid tumors, particularly after exposure to radiation and chemotherapy. CHIP testing may inform risk-reduction strategies for cancer survivors. Little is known about patient knowledge, attitudes, and preferences regarding CHIP testing. Methods: We surveyed survivors without history of recurrence participating in an ongoing prospective cohort study of young women with breast cancer (BC). The survey was sent by email and included an introduction to CHIP including risk factors and clinical associations. Respondents then reviewed a vignette and were asked about CHIP testing preferences (definitely/probably test vs. definitely/probably not test) considering sequentially: 1) population-based 10-year risk of BC recurrence, hematological malignancy and heart disease; 2) estimated increase in these risks with CHIP; 3) current CHIP management; 4) a dedicated CHIP clinic; and 5) a theoretical CHIP treatment. Changes in preferences from the prior scenario were evaluated with the McNemar's test using a type I error rate of 5%. Results: 528/642 (82.2%) eligible women responded to the survey, at a median age of 46 (range: 31-54) years (median time from diagnosis: 108 months (range: 60-168)), and 88% were white. Most had stage 1/2 BC (78.8%) and had received chemotherapy (73.1%) and/or radiation (61.9%). 93.6% had never heard of CHIP prior to survey. After initial patient vignette presentation, most women (87.1%,) recommended CHIP testing if offered. Preferences for testing decreased (p<0.05) when considering population-based risks, with 11.1% shifting their preference from CHIP testing to not testing. After considering increased risks associated with CHIP, interest in testing increased (p<0.05), with 10.1% shifting their preference to testing. Interest significantly (p<0.05) increased with the possibility of managing CHIP through a clinic or a hypothetical CHIP treatment, with 7.2% and 14.1% switching their preferences towards testing, respectively. Finally, 75.8% responded that they themselves, after learning about CHIP and reviewing the vignette, would want to have CHIP testing; 28.2% reported that learning about CHIP and the associated risks caused them at least moderate anxiety. Conclusion: Few young BC survivors were aware of CHIP yet most indicated an interest in testing after learning about it. Testing preferences were influenced by risks presented and potential management strategies. Findings highlight the importance of effective risk communication and the need for adequate psychosocial support when considering testing for CHIP and other potential clinical biomarkers predictive of cancer and other medical risks in cancer survivors.

On-Chip Assessment of Scattering in the Response of Si-Based Microdevices

The response of micromachines to the external actions is typically affected by a scattering, which is, on its own, induced by their microstructure and by stages of the microfabrication process. The progressive reduction in size of the mechanical components, forced by a path towards (further) miniaturization, has recently enhanced the outcomes of the aforementioned scattering, and provided a burst in research activities to address issues linked to its assessment. In this work, we discuss the features of an on-chip testing device that we purposely designed to efficiently estimate the two major sources of scattering affecting inertial, polysilicon-based micromachines: the morphology of the silicon film constituting the movable parts of the device, and the etch defect or over-etch induced by microfabrication. The coupled electro-mechanical behavior of the statically determinate movable (micro)structure of the on-chip device has been modeled via beam bending theory, within which the aforementioned sources of scattering have been accounted for through local fluctuating fields in the compliant part of the structure itself, namely the supporting spring. The proposed stochastic model is shown to outperform former ones available in the literature, which neglected the simultaneous and interacting effects of the two mentioned sources on the measure response. The model can fully catch the scattering in the C–V plots up to pull-in, hence, also in the nonlinear working regime of the device.

A Deep Learning-Based Approach to Uncertainty Quantification for Polysilicon MEMS

The path towards miniaturization for micro-electro-mechanical systems (MEMS) has recently increased the effects of stochastic variability at the (sub)micron scale on the overall performance of the devices. We recently proposed and designed an on-chip testing device to characterize two sources of variability that majorly affect the scattering in response to the external actions of inertial (statically determinate) micromachines: the morphology of the polysilicon film constituting the movable parts of the device, and the environment-affected over-etch linked to the microfabrication process. A fully stochastic model of the entire device has been set to account for these two sources on the measurable response of the devices, e.g., in terms of the relevant C-V curves up to pull-in. A complexity in the mentioned model is represented by the need to assess the stochastic (local) stiffness of polysilicon, depending on its unknown (local) microstructure. In this work, we discuss a deep learning approach to the micromechanical characterization of polysilicon films, based on densely connected neural networks (NNs). Such NNs extract relevant features of the polysilicon morphology from SEM-like Voronoi tessellation-based digital microstructures. The NN-based model or surrogate is shown to correctly catch size effects at a varying ratio between the characteristic size of the structural components of the device, and the morphology-induced length scale of the aggregate of silicon grains. This property of the model looks to indeed be necessary to prove the generalization capability of the learning process, and to next feed Monte Carlo simulations resting on the model of the entire device.

A Stochastic Model to Describe the Scattering in the Response of Polysilicon MEMS

The current miniaturization trend in the market of inertial microsystems is leading to movable device parts with sizes comparable to the characteristic length-scale of the polycrystalline silicon film morphology. The relevant output of micro electro-mechanical systems (MEMS) is thus more and more affected by a scattering, induced by features resulting from the micro-fabrication process. We recently proposed an on-chip testing device, specifically designed to enhance the aforementioned scattering in compliance with fabrication constraints. We proved that the experimentally measured scattering cannot be described by allowing only for the morphology-affected mechanical properties of the silicon films, and etch defects must be properly accounted for too. In this work, we discuss a fully stochastic framework allowing for the local fluctuations of the stiffness and of the etch-affected geometry of the silicon film. The provided semi-analytical solution is shown to catch efficiently the measured scattering in the C-V plots collected through the test structure. This approach opens up the possibility to learn on-line specific features of the devices, and to reduce the time required for their calibration.

Improving Compression Ratios for Code-Based Test Pattern Compressions through Column-Wise Reordering Algorithms

Chip testing is an effective way to reduce the number of defective or faulty chips that reach the market. However, as large-scale test patterns need to be transmitted into a circuit under test during testing, the transmission time dominates the test application time of the chip testing. Therefore, code-based compression methods are widely used in compressing test patterns because of their capability to reduce the transmission time and save storage space significantly. Current code-based compression methods cannot fully apply the inherent characteristics of test patterns yet. To address this problem, this study proposes two-stage test pattern preprocessing algorithms, thereby improving the efficiency of the code-based compression method. First, we propose a column-wise reordering for Hadamard matrix (CRHM) algorithm, which decomposes a test set consisting of test patterns into a primary component set (PCS) and a residual component set (RCS). The PCS inherits some 1s from the original test set (OTS), and other 1s belong to the RCS. As the number of 1s contained in the RCS is less than that in the OTS, the RCS can obtain a higher code-based compression ratio. The PCS can be generated by an on-chip generator, which does not consume transmission time. Second, we propose a novel column-wise reordering for the RCS (CRRCS) algorithm. The CRRCS solves the new location of each column of the RCS one by one in the list to decrease the entropy of the RCS. The entropy denotes the shortest length of the codeword required for the symbol to be encoded. The smaller entropy value refers to a higher compression ratio. For the sorted RCS, more high-frequency symbols can be replaced by shorter codewords. Experimental results based on seven code-based compression methods show that the proposed algorithms can increase the average compression ratio by a total of 19.91%, and the highest average compression ratio reaches 85.04% for ISCAS’89 benchmark circuits.

Implementation of Analog Perceptron as an Essential Element of Configurable Neural Networks

Perceptron is an essential element in neural network (NN)-based machine learning, however, the effectiveness of various implementations by circuits is rarely demonstrated from chip testing. This paper presents the measured silicon results for the analog perceptron circuits fabricated in a 0.6 μm/±2.5 V complementary metal oxide semiconductor (CMOS) process, which are comprised of digital-to-analog converter (DAC)-based multipliers and phase shifters. The results from the measurement convinces us that our implementation attains the correct function and good performance. Furthermore, we propose the multi-layer perceptron (MLP) by utilizing analog perceptron where the structure and neurons as well as weights can be flexibly configured. The example given is to design a 2-3-4 MLP circuit with rectified linear unit (ReLU) activation, which consists of 2 input neurons, 3 hidden neurons, and 4 output neurons. Its experimental case shows that the simulated performance achieves a power dissipation of 200 mW, a range of working frequency from 0 to 1 MHz, and an error ratio within 12.7%. Finally, to demonstrate the feasibility and effectiveness of our analog perceptron for configuring a MLP, seven more analog-based MLPs designed with the same approach are used to analyze the simulation results with respect to various specifications, in which two cases are used to compare to their digital counterparts with the same structures.

Automatic chip testing system

In this paper, we implement an automatic chip testing system which can be applied on various types of chip packages. The conventional systems, such as manual chip testing systems, often repeat the same steps for input conditions; or high-cost testing systems are designed to be highly optimized, but the installation and operating costs are very expensive. This makes these systems difficult to be applied in education, research or small companies. The automatic chip testing system overcomes the above two weaknesses. The proposed system not only meets the requirement of a basic chip testing process, but also operates automatically and reduces the cost. Users only need to provide input data via a Graphical User Interface (GUI) which is built using C# programming language, then the system will automatically operate and return the corresponding output data to the software to synthesize and compare with the user’s expected data. The hardware is built on the TR4 FPGA Development Kit which helps save the cost of hardware design and its resources. The software and hardware withcommunicate to each other via Universal Asynchronous Receiver-Transmitter (UART) protocol. The proposed system is automatic, optimized and low-cost so that it can be applied both in IC design education and industry.