Shallow Trench Isolation Chemical Mechanical Planarization: A Review

2015 ◽  
Vol 4 (11) ◽  
pp. P5029-P5039 ◽  
Author(s):  
Ramanathan Srinivasan ◽  
Pradeep VR Dandu ◽  
S. V. Babu
Keyword(s):  
Chemical Mechanical Planarization ◽  
Shallow Trench Isolation ◽  
Trench Isolation

Advances in Chemical-Mechanical Planarization

MRS Bulletin ◽  
2002 ◽  
Vol 27 (10) ◽  
pp. 743-751 ◽  
Author(s):  
Rajiv K. Singh ◽  
Rajeev Bajaj
Keyword(s):  
Surface Topography ◽  
Process Integration ◽  
Semiconductor Industry ◽  
Chemical Mechanical Planarization ◽  
Shallow Trench Isolation ◽  
Trench Isolation ◽  
Fundamental Understanding ◽  
Copper Polishing ◽  
Future Growth

AbstractThe primary aim of this issue of MRS Bulletin is to present an overview of the materials issues in chemical–mechanical planarization (CMP), also known as chemical–mechanial polishing, a process that is used in the semiconductor industry to isolate and connect individual transistors on a chip. The CMP process has been the fastest-growing semiconductor operation in the last decade, and its future growth is being fueled by the introduction of copper-based interconnects in advanced microprocessors and other devices. Articles in this issue range from providing a fundamental understanding of the CMP process to the latest advancements in the field. Topics covered in these articles include an overview of CMP, fundamental principles of slurry design, understanding wafer–pad–slurry interactions, process integration issues, the formulation of abrasive-free slurries for copper polishing, understanding surface topography issues in shallow trench isolation, and emerging applications.

Electrical AFM Measurements for Evaluation of Nitride Erosion in Shallow Trench Isolation Chemical Mechanical Planarization

2004 ◽  
Vol 838 ◽  
Author(s):  
Yordan Stefanov ◽  
Tino Ruland ◽  
Udo Schwalke
Keyword(s):  
Chemical Mechanical Planarization ◽  
Tunneling Current ◽  
Silicon Surfaces ◽  
Nanometer Scale ◽  
Shallow Trench Isolation ◽  
Force Microscopy ◽  
Atomic Force ◽  
Trench Isolation ◽  
Clear Identification ◽  
Non Destructive

ABSTRACTThis article proposes a new application of tunneling current measurements Atomic Force Microscopy (AFM) for evaluation of silicon nitride stop-layer erosion in Shallow Trench Isolation (STI) Chemical Mechanical Planarization (CMP). Simultaneous topographical and electrical AFM measurements allow a clear identification of ‘open’ silicon surfaces on nanometer scale by enhanced tunneling currents in those areas. The measurement technique is non-destructive and can be successfully implemented for process control.

Nanotopography Issues in Shallow Trench Isolation CMP

MRS Bulletin ◽  
2002 ◽  
Vol 27 (10) ◽  
pp. 761-765 ◽  
Author(s):  
Duane Boning ◽  
Brian Lee
Keyword(s):  
Integrated Circuits ◽  
Chemical Mechanical Planarization ◽  
Surface Films ◽  
Small Surface ◽  
Shallow Trench Isolation ◽  
Important Concern ◽  
Trench Isolation ◽  
Time Required ◽  
Nitride Layers ◽  
Cmp Model

AbstractAs advancing technologies increase the demand for planarity in integrated circuits, nanotopography has emerged as an important concern in shallow trench isolation (STI) on wafers polished by means of chemical–mechanical planarization (CMP). Previous work has shown that nanotopography—small surface-height variations of 10–100 nm in amplitude extending across millimeter-scale lateral distances on virgin wafers—can result in CMP-induced localized thinning of surface films such as the oxides or nitrides used in STI. A contact-wear CMP model can be employed to produce maps of regions on a given starting wafer that are prone to particular STI failures, such as the lack of complete clearing of the oxide in low spots and excessive erosion of nitride layers in high spots on the wafer. Stiffer CMP pads result in increased nitride thinning. A chip-scale pattern-dependent CMP simulation shows that substantial additional dishing and erosion occur because of the overpolishing time required due to nanotopography. Projections indicate that nanotopography height specifications will likely need to decrease in order to scale with smaller feature sizes in future IC technologies.

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