Advances in Chemical-Mechanical Planarization

MRS Bulletin ◽  
2002 ◽  
Vol 27 (10) ◽  
pp. 743-751 ◽  
Author(s):  
Rajiv K. Singh ◽  
Rajeev Bajaj
Keyword(s):  
Surface Topography ◽  
Process Integration ◽  
Semiconductor Industry ◽  
Chemical Mechanical Planarization ◽  
Shallow Trench Isolation ◽  
Trench Isolation ◽  
Fundamental Understanding ◽  
Copper Polishing ◽  
Future Growth

AbstractThe primary aim of this issue of MRS Bulletin is to present an overview of the materials issues in chemical–mechanical planarization (CMP), also known as chemical–mechanial polishing, a process that is used in the semiconductor industry to isolate and connect individual transistors on a chip. The CMP process has been the fastest-growing semiconductor operation in the last decade, and its future growth is being fueled by the introduction of copper-based interconnects in advanced microprocessors and other devices. Articles in this issue range from providing a fundamental understanding of the CMP process to the latest advancements in the field. Topics covered in these articles include an overview of CMP, fundamental principles of slurry design, understanding wafer–pad–slurry interactions, process integration issues, the formulation of abrasive-free slurries for copper polishing, understanding surface topography issues in shallow trench isolation, and emerging applications.

Current Issues and Future Trends in CMP Consumables for Oxide and Metal Polish

1996 ◽  
Vol 427 ◽  
Author(s):  
M. Moinpour ◽  
A. Philipossian
Keyword(s):  
Semiconductor Industry ◽  
Chemical Mechanical Planarization ◽  
Future Trends ◽  
Process Technology ◽  
Shallow Trench Isolation ◽  
Current Trends ◽  
Front End ◽  
Technological Advantage ◽  
Trench Isolation ◽  
Major Process

IntroductionThe recent advent of Chemical Mechanical Planarization (CMP) as a major process technology has had a significant impact on the semiconductor industry. Oxide CMP is a technology enabler for logic and DRAM devices with feature sizes less than (or equal to) 0.75 micrometer [1]. Similarly, tungsten CMP has become a technology enabler for 0.35 micron devices [2,3], and current trends indicate that it will continue to play a major role in future generations of IC technologies [4,5]. CMP can also provide a technological advantage in front-end process modules such as Shallow Trench Isolation [6].

Journey Toward Process Convergence in TSV Technology

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 001282-001321
Author(s):  
Sesh Ramaswami ◽  
John Dukovic
Keyword(s):  
Process Integration ◽  
Semiconductor Industry ◽  
Rapid Development ◽  
Chemical Mechanical Planarization ◽  
Cost Effective ◽  
Superior Performance ◽  
Wafer Level ◽  
Unit Process ◽  
Integration Schemes ◽  
Process Convergence

Continuous demand for more advanced electronic devices with higher functionality and superior performance in smaller packages is driving the semiconductor industry to develop new and more advanced 3D wafer-level interconnect technologies involving TSVs (through-silicon vias). The TSVs are created either on full-thickness wafer from the wafer front-side ¡V as part of wafer-fab processing during Middle-Of-Line (¡§via middle¡¨) or Back-End-Of-Line (¡§via last BEOL¡¨) ¡V or from the wafer backside after wafer thinning (¡§via last backside¡¨). Independent of the specific approach, the main steps include via etching, lining with insulator, copper barrier/seed deposition, via fill, and chemical mechanical planarization (CMP). Over the past year, the industry has been converging toward some primary unit processes and integration schemes for creating the TSVs. A common cost-of-ownership framework has also begun to emerge. Active collaboration underway among equipment suppliers, materials providers and end users is bringing about rapid development and validation of cost-effective TSV technology in end products. This presentation will address unit-process and integration challenges of TSV fabrication in the context of 20x100ƒÝm and 5x50ƒÝm baseline process flows at Applied Materials. Highlights of wafer-backside process integration involving wafers bonded to silicon or glass carriers will also be discussed.

Shallow Trench Isolation Chemical Mechanical Planarization: A Review

2015 ◽  
Vol 4 (11) ◽  
pp. P5029-P5039 ◽  
Author(s):  
Ramanathan Srinivasan ◽  
Pradeep VR Dandu ◽  
S. V. Babu
Keyword(s):  
Chemical Mechanical Planarization ◽  
Shallow Trench Isolation ◽  
Trench Isolation

Relating Friction in CMP to Topography Evolution

2005 ◽  
Author(s):  
Xiaolin Xie ◽  
Duane Boning
Keyword(s):  
Surface Topography ◽  
Integrated Circuit ◽  
Friction And Wear ◽  
Shallow Trench Isolation ◽  
Integrated Circuit Manufacturing ◽  
Scale Models ◽  
Trench Isolation ◽  
Model Predictions ◽  
Different Types ◽  
Dual Material

Die-scale models of chemical-mechanical polishing (CMP) have been previously reported for a number of different CMP processes used in integrated circuit manufacturing, including oxide, dual material shallow trench isolation, and dual material copper damascene processes. These models can dynamically predict the evolution of surface topography (e.g., local feature step heights, film thickness nonuniformity across the different pattern density regions of the chip, dishing, and erosion) for any time point during CMP. This topography evolution information can be applied to better understand the basis for observed friction and wear in the CMP process. In this work, we explore models of the macroscopic frictional force based on the surface topography. CMP endpoint measurements, such as those from motor current traces, enable verification of model predictions relating friction to CMP surface topography evolution, for different types of CMP processes and patterned chips.

Sign in / Sign up

Export Citation Format

Share Document