scholarly journals The STC104 Packet Routing Chip

VLSI Design ◽  
1995 ◽  
Vol 2 (4) ◽  
pp. 305-314 ◽  
Author(s):  
Peter W. Thompson ◽  
Julian D. Lewis
Keyword(s):  
High Performance ◽  
Design Methodology ◽  
Parallel Systems ◽  
System Size ◽  
General Purpose ◽  
Packet Routing ◽  
Design Issues ◽  
Exchange Data

High-performance parallel systems demand a high-performance interconnect so that their component parts can exchange data and synchronise efficiently. The interconnect must be cheap, and must also scale well in both performance and cost relative to the system size. In this paper we describe the rationale, architecture and operation of the STC104, the first commercially available, general-purpose interconnect chip. The serial protocols used by the device are described, followed by an overview of the microarchitecture, The operation of the fundamental block is outlined, including the response to error conditions. Chip-wide design issues and design methodology are discussed, and finally various aspects of performance are calculated.

scholarly journals Multi-Softcore Architecture on FPGA

2014 ◽  
Vol 2014 ◽  
pp. 1-13 ◽  
Author(s):  
Mouna Baklouti ◽  
Mohamed Abid
Keyword(s):  
High Performance ◽  
Design Methodology ◽  
Matrix Multiplication ◽  
Rapid Prototype ◽  
General Purpose ◽  
Parallel Applications ◽  
Multicore Systems ◽  
Processor Core ◽  
Nios Ii ◽  
Wide Range

To meet the high performance demands of embedded multimedia applications, embedded systems are integrating multiple processing units. However, they are mostly based on custom-logic design methodology. Designing parallel multicore systems using available standards intellectual properties yet maintaining high performance is also a challenging issue. Softcore processors and field programmable gate arrays (FPGAs) are a cheap and fast option to develop and test such systems. This paper describes a FPGA-based design methodology to implement a rapid prototype of parametric multicore systems. A study of the viability of making the SoC using the NIOS II soft-processor core from Altera is also presented. The NIOS II features a general-purpose RISC CPU architecture designed to address a wide range of applications. The performance of the implemented architecture is discussed, and also some parallel applications are used for testing speedup and efficiency of the system. Experimental results demonstrate the performance of the proposed multicore system, which achieves better speedup than the GPU (29.5% faster for the FIR filter and 23.6% faster for the matrix-matrix multiplication).

A DESIGN METHODOLOGY FOR VERY LARGE ARRAY PROCESSORS—PART 1: GIPOP PROCESSOR ARRAY

1995 ◽  
Vol 09 (02) ◽  
pp. 231-262
Author(s):  
N. VENKATESWARAN ◽  
S. PATTABIRAMAN ◽  
R. DEVANATHAN ◽  
B. KUMARAN ◽  
ASHRAF AHMED ◽  
...  
Keyword(s):  
High Performance ◽  
Design Methodology ◽  
General Purpose ◽  
Massively Parallel ◽  
Inner Product ◽  
Processor Array ◽  
Large Array ◽  
Outer Product ◽  
Very Large Array ◽  
Array Processors

Very Large Array Processors (VLAP) will be the need of the future for solving computationally intense Very Large Problems (VLP) common in pattern recognition, image processing and other related areas of digital signal processing. Design methodology of such VLAPs for massively parallel dedicated/general purpose applications is highly complex. Two companion papers (Part 1 and Part 2) on VLAP are presented in this issue. In Part 1, we propose a VLAP called Reconfigurable GIPOP Processor Array (RGPA). The RGPA is made up of high performance processing elements called the Generalized Inner Product Outer Product (GIPOP) processor. Unlike the traditional special/general purpose processors, ours has a totally different and new architecture and organization involving higher level functional units to match with the complex computational structures of numeric algorithms and suitable for massively parallel processing. We also present a strategy for mapping VLPs on VLAPs. In Part 2, we propose a novel VLSI design methodology for implementing cost effective and very high performance processors meant for special purpose applications and in particular, for VLAPs.

Design Tradeoffs of High Performance DSPs for General-Purpose HPC

2014 ◽  
Vol 36 (4) ◽  
pp. 790-798
Author(s):  
Kai ZHANG ◽  
Shu-Ming CHEN ◽  
Yao-Hua WANG ◽  
Xi NING
Keyword(s):  
High Performance ◽  
General Purpose ◽  
Design Tradeoffs

CHASSIS DESIGN & PERFORMANCE ANALYSIS FOR THE EUROPEAN EXOMARS ROVER

2005 ◽  
Vol 29 (4) ◽  
pp. 507-517
Author(s):  
Alex Ellery ◽  
Lutz Richter ◽  
Reinhold Bertrand
Keyword(s):  
Performance Analysis ◽  
Weight Distribution ◽  
High Performance ◽  
High Mobility ◽  
Scientific Instrument ◽  
Equal Weight ◽  
Scientific Instruments ◽  
Design Issues ◽  
Martian Surface ◽  
Considerable Size

The European Space Agency’s (ESA) ExoMars rover has recently been subject to a Phase A study led by EADS Astrium, UK. This rover mission represents a highly ambitious venture in that the rover is of considerable size ~200+kg with high mobility carrying a highly complex scientific instrument suite (Pasteur) of up to 40 kg in mass devoted to exobiological investigation of the Martian surface and sub-surface. The chassis design has been a particular challenge given the inhospitable terrain on Mars and the need to traverse such terrain robustly in order to deliver the scientific instruments to science targets of exobiological interest, We present some of the results and design issues encountered during the Phase A study related to the chassis. In particular, we have focussed on the overall tractive performance of a number of candidate chassis designs and selected the RCL (Science & Technology Rover Company Ltd in Russian) concept C design as the baseline option in terms of high performance with minimal mechanical complexity overhead. This design is a six-wheeled double-rocker bogie design to provide springless suspension and maintain approximately equal weight distribution across each wheel.

scholarly journals DSPSR: Digital Signal Processing Software for Pulsar Astronomy

2011 ◽  
Vol 28 (1) ◽  
pp. 1-14 ◽  
Author(s):  
W. van Straten ◽  
M. Bailes
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Graphics Processing Units ◽  
High Performance ◽  
Digital Signal ◽  
General Purpose ◽  
Design Decisions ◽  
Extensive Range ◽  
Processing Software ◽  
Graphics Processing

Abstractdspsr is a high-performance, open-source, object-oriented, digital signal processing software library and application suite for use in radio pulsar astronomy. Written primarily in C++, the library implements an extensive range of modular algorithms that can optionally exploit both multiple-core processors and general-purpose graphics processing units. After over a decade of research and development, dspsr is now stable and in widespread use in the community. This paper presents a detailed description of its functionality, justification of major design decisions, analysis of phase-coherent dispersion removal algorithms, and demonstration of performance on some contemporary microprocessor architectures.

High-Performance Motion Control With Slosh: A Constrained Sliding Mode Approach

2008 ◽  
Author(s):  
Hanz Richter ◽  
Kedar B. Karnik
Keyword(s):  
High Speed ◽  
High Performance ◽  
Design Methodology ◽  
Closed Loop ◽  
Sliding Mode ◽  
Initial Conditions ◽  
Rectilinear Motion ◽  
Industrial Setting ◽  
Open Container ◽  
Nominal Performance

The problem of controlling the rectilinear motion of an open container without exceeding a prescribed liquid level and other constraints is considered using a recently-developed constrained sliding mode control design methodology based on invariant cylinders. A conventional sliding mode regulator is designed first to address nominal performance in the sliding mode. Then an robustly-invariant cylinder is constructed and used to describe the set of safe initial conditions from which the closed-loop controller can be operated without constraint violation. Simulations of a typical transfer illustrate the usefulness of the method in an industrial setting. Experimental results corresponding to a high-speed transfer validate the theory.

Stochastic comparisons of series and parallel systems with independent heterogeneous Gumbel and truncated Gumbel components

2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Fatih Kızılaslan
Keyword(s):  
Likelihood Ratio ◽  
Hazard Rate ◽  
Design Methodology ◽  
Parallel Systems ◽  
Parallel System ◽  
Series System ◽  
Stochastic Comparisons ◽  
Content Type ◽  
Reversed Hazard Rate ◽  
The Relationship

PurposeThe purpose of this paper is to investigate the stochastic comparisons of the parallel system with independent heterogeneous Gumbel components and series and parallel systems with independent heterogeneous truncated Gumbel components in terms of various stochastic orderings.Design/methodology/approachThe obtained results in this paper are obtained by using the vector majorization methods and results. First, the components of series and parallel systems are heterogeneous and having Gumbel or truncated Gumbel distributions. Second, multiple-outlier truncated Gumbel models are discussed for these systems. Then, the relationship between the systems having Gumbel components and Weibull components are considered. Finally, Monte Carlo simulations are performed to illustrate some obtained results.FindingsThe reversed hazard rate and likelihood ratio orderings are obtained for the parallel system of Gumbel components. Using these results, similar new results are derived for the series system of Weibull components. Stochastic comparisons for the series and parallel systems having truncated Gumbel components are established in terms of hazard rate, likelihood ratio and reversed hazard rate orderings. Some new results are also derived for the series and parallel systems of upper-truncated Weibull components.Originality/valueTo the best of our knowledge thus far, stochastic comparisons of series and parallel systems with Gumbel or truncated Gumble components have not been considered in the literature. Moreover, new results for Weibull and upper-truncated Weibull components are presented based on Gumbel case results.

“It's the work climate that keeps me here”: the interplay between the HRM process and emergent factors in the construction of employee experiences

2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Maarit Laiho ◽  
Essi Saru ◽  
Hannele Seeck
Keyword(s):  
High Performance ◽  
Design Methodology ◽  
Qualitative Interview ◽  
Employee Perceptions ◽  
Content Type ◽  
Systematic Data ◽  
High Performance Work System ◽  
Employee Experience ◽  
The Relationship ◽  
Shed Light

PurposeThe purpose of this paper is to explore the interplay between human resource management (HRM) and emergent factors in constructing a strong HRM climate. Specifically, the paper aims to shed light on how employee perceptions of the HRM process and emergent factors together construct a strong HRM climate, i.e. employees' shared perceptions of HRM.Design/methodology/approachThe paper uses qualitative interview data (managers and employees) from two organisations operating in Finland. The data are analysed based on a systematic data analysis and gives an illustration of the interplay between high-performance work system and the emergent factors.FindingsThe findings illustrate the three types of interplay between HPWS and emergent factors – supplementation, substitution and suffocation – that construct employee experience.Originality/valueThe paper extends earlier discussions on the relationship between HRM and employee experience by empirically examining how the HRM process – together with emergent factors – constructs a strong HRM climate. The present study contributes to further theorising and increasing our understanding of the creation of employee experience.

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