scholarly journals Logic Synthesis for a Regular Layout

VLSI Design ◽  
1999 ◽  
Vol 10 (1) ◽  
pp. 35-55 ◽  
Author(s):  
Malgorzata Chrzanowska-Jeske ◽  
Yang Xu ◽  
Marek Perkowski
Keyword(s):  
Boolean Functions ◽  
Symmetric Functions ◽  
Logic Synthesis ◽  
Regular Structure ◽  
Theoretical Background ◽  
Device Performance ◽  
Decision Diagrams ◽  
Binary Decision ◽  
Function Representation ◽  
New Algorithms

New algorithms for generating a regular two-dimensional layout representation for multi-output, incompletely specified Boolean functions, called, Pseudo-Symmetric Binary Decision Diagrams (PSBDDs), are presented. The regular structure of the function representation allows accurate prediction of post-layout areas and delays before the layout is physically generated. It simplifies power estimation on the gate level and allows for more accurate power optimization. The theoretical background of the new diagrams, which are based on ideas from contact networks, and the form of decision diagrams for symmetric functions is discussed. PSBDDs are especially well suited for deep sub-micron technologies where the delay of interconnections limits the device performance. Our experimental results are very good and show that symmetrization of reallife benchmark functions can be done efficiently.

scholarly journals A Novel Graphical Technique for Combinational Logic Representation and Optimization

Complexity ◽  
2017 ◽  
Vol 2017 ◽  
pp. 1-12
Author(s):  
Vedhas Pandit ◽  
Björn Schuller
Keyword(s):  
Boolean Functions ◽  
Discrete Systems ◽  
Boolean Logic ◽  
Decision Diagrams ◽  
New Paradigm ◽  
Binary Decision ◽  
Graphical Technique ◽  
A New Technique ◽  
Logic Functions ◽  
Logical Functions

We present a new technique for defining, analysing, and simplifying digital functions, through hand-calculations, easily demonstrable therefore in the classrooms. It can be extended to represent discrete systems beyond the Boolean logic. The method is graphical in nature and provides complete ‘‘implementation-free” description of the logical functions, similar to binary decision diagrams (BDDs) and Karnaugh-maps (K-maps). Transforming a function into the proposed representations (also the inverse) is a very intuitive process, easy enough that a person can hand-calculate these transformations. The algorithmic nature allows for its computing-based implementations. Because the proposed technique effectively transforms a function into a scatter plot, it is possible to represent multiple functions simultaneously. Usability of the method, therefore, is constrained neither by the number of inputs of the function nor by its outputs in theory. This, being a new paradigm, offers a lot of scope for further research. Here, we put forward a few of the strategies invented so far for using the proposed representation for simplifying the logic functions. Finally, we present extensions of the method: one that extends its applicability to multivalued discrete systems beyond Boolean functions and the other that represents the variants in terms of the coordinate system in use.

scholarly journals An n log n Algorithm for Online BDD Refinement

1995 ◽  
Vol 2 (29) ◽  
Author(s):  
Nils Klarlund
Keyword(s):  
Fixed Points ◽  
Boolean Functions ◽  
Linear Time ◽  
Canonical Representation ◽  
Decision Diagrams ◽  
Total Size ◽  
Binary Decision ◽  
Algebraic Framework ◽  
Verification Systems ◽  
Minimal Fixed Point

Binary Decision Diagrams are in widespread use in verification systems<br />for the canonical representation of Boolean functions. A BDD representing<br />a function phi : B^nu -> N can easily be reduced to its canonical form in<br />linear time.<br />In this paper, we consider a natural online BDD refinement problem<br />and show that it can be solved in O(n log n) if n bounds the size of the<br />BDD and the total size of update operations.<br />We argue that BDDs in an algebraic framework should be understood<br />as minimal fixed points superimposed on maximal fixed points. We propose<br />a technique of controlled growth of equivalence classes to make the<br />minimal fixed point calculations be carried out efficiently. Our algorithm<br />is based on a new understanding of the interplay between the splitting<br />and growing of classes of nodes.<br />We apply our algorithm to show that automata with exponentially<br />large, but implicitly represented alphabets, can be minimized in time<br />O(n log n), where n is the total number of BDD nodes representing the<br />automaton.

scholarly journals Decomposition-based logic synthesis for PAL-based CPLDs

2010 ◽  
Vol 20 (2) ◽  
pp. 367-384 ◽  
Author(s):  
Adam Opara ◽  
Dariusz Kania
Keyword(s):  
Binary Decision Diagrams ◽  
Logic Synthesis ◽  
Decomposition Methods ◽  
Decision Diagrams ◽  
Two Stage ◽  
Ordered Binary Decision Diagrams ◽  
Binary Decision ◽  
Single Output ◽  
Programmable Device ◽  
Logic Blocks

Decomposition-based logic synthesis for PAL-based CPLDsThe paper presents one concept of decomposition methods dedicated to PAL-based CPLDs. The proposed approach is an alternative to the classical one, which is based on two-level minimization of separate single-output functions. The key idea of the algorithm is to search for free blocks that could be implemented in PAL-based logic blocks containing a limited number of product terms. In order to better exploit the number of product terms, two-stage decomposition and BDD-based decomposition are to be used. In BDD-based decomposition methods, functions are represented by Reduced Ordered Binary Decision Diagrams (ROBDDs). The results of experiments prove that the proposed solution is more effective, in terms of the usage of programmable device resources, compared with the classical ones.

scholarly journals Multi-Level Logic Synthesis Based on Kronecker Decision Diagrams and Boolean Ternary Decision Diagrams for Incompletely Specified Functions

VLSI Design ◽  
1995 ◽  
Vol 3 (3-4) ◽  
pp. 301-313 ◽  
Author(s):  
Marek A. Perkowski ◽  
Malgorzata Chrzanowska-Jeske ◽  
Andisheh Sarabi ◽  
Ingo Schäfer
Keyword(s):  
Boolean Functions ◽  
Logic Synthesis ◽  
General Purpose ◽  
Compact Representation ◽  
Decision Diagrams ◽  
Circuit Realization ◽  
Orthogonal Expansions ◽  
Fine Grain ◽  
Multi Level ◽  
Don't Cares

This paper introduces several new families of decision diagrams for multi-output Boolean functions. The introduced families include several diagrams known from literature (BDDs, FDDs) as subsets. Due to this property, these diagrams can provide a more compact representation of functions than either of the two decision diagrams. Kronecker Decision Diagrams (KDDs) with negated edges are based on three orthogonal expansions (Shannon, Positive Davio, Negative Davio) and are created here for incompletely specified Boolean functions as well. An improved efficient algorithm for the construction of KDD is presented and applied in a mapping program to ATMEL 6000 fine-grain FPGAs. Four other new families of functional decision diagrams are also presented: Pseudo KDDs, Free KDDs, Boolean Ternary DDs, and Boolean Kronecker Ternary DDs. The last two families introduce nodes with three edges and require AND, OR and EXOR gates for circuit realization. There are two variants of each of the last two families: canonical and non-canonical. While the canonical diagrams can be used as efficient general-purpose Boolean function representations, the non-canonical variants are also applicable to incompletely specified functions and create don't cares in the process of the creation of the diagram.. They lead to even more compact circuits in logic synthesis and technology mapping.

Sign in / Sign up

Export Citation Format

Share Document