scholarly journals Multi-Level Logic Synthesis Based on Kronecker Decision Diagrams and Boolean Ternary Decision Diagrams for Incompletely Specified Functions

VLSI Design ◽  
1995 ◽  
Vol 3 (3-4) ◽  
pp. 301-313 ◽  
Author(s):  
Marek A. Perkowski ◽  
Malgorzata Chrzanowska-Jeske ◽  
Andisheh Sarabi ◽  
Ingo Schäfer
Keyword(s):  
Boolean Functions ◽  
Logic Synthesis ◽  
General Purpose ◽  
Compact Representation ◽  
Decision Diagrams ◽  
Circuit Realization ◽  
Orthogonal Expansions ◽  
Fine Grain ◽  
Multi Level ◽  
Don't Cares

This paper introduces several new families of decision diagrams for multi-output Boolean functions. The introduced families include several diagrams known from literature (BDDs, FDDs) as subsets. Due to this property, these diagrams can provide a more compact representation of functions than either of the two decision diagrams. Kronecker Decision Diagrams (KDDs) with negated edges are based on three orthogonal expansions (Shannon, Positive Davio, Negative Davio) and are created here for incompletely specified Boolean functions as well. An improved efficient algorithm for the construction of KDD is presented and applied in a mapping program to ATMEL 6000 fine-grain FPGAs. Four other new families of functional decision diagrams are also presented: Pseudo KDDs, Free KDDs, Boolean Ternary DDs, and Boolean Kronecker Ternary DDs. The last two families introduce nodes with three edges and require AND, OR and EXOR gates for circuit realization. There are two variants of each of the last two families: canonical and non-canonical. While the canonical diagrams can be used as efficient general-purpose Boolean function representations, the non-canonical variants are also applicable to incompletely specified functions and create don't cares in the process of the creation of the diagram.. They lead to even more compact circuits in logic synthesis and technology mapping.

scholarly journals Logic Synthesis for a Regular Layout

VLSI Design ◽  
1999 ◽  
Vol 10 (1) ◽  
pp. 35-55 ◽  
Author(s):  
Malgorzata Chrzanowska-Jeske ◽  
Yang Xu ◽  
Marek Perkowski
Keyword(s):  
Boolean Functions ◽  
Symmetric Functions ◽  
Logic Synthesis ◽  
Regular Structure ◽  
Theoretical Background ◽  
Device Performance ◽  
Decision Diagrams ◽  
Binary Decision ◽  
Function Representation ◽  
New Algorithms

New algorithms for generating a regular two-dimensional layout representation for multi-output, incompletely specified Boolean functions, called, Pseudo-Symmetric Binary Decision Diagrams (PSBDDs), are presented. The regular structure of the function representation allows accurate prediction of post-layout areas and delays before the layout is physically generated. It simplifies power estimation on the gate level and allows for more accurate power optimization. The theoretical background of the new diagrams, which are based on ideas from contact networks, and the form of decision diagrams for symmetric functions is discussed. PSBDDs are especially well suited for deep sub-micron technologies where the delay of interconnections limits the device performance. Our experimental results are very good and show that symmetrization of reallife benchmark functions can be done efficiently.

scholarly journals Bi-Kronecker Functional Decision Diagrams: A Novel Canonical Representation of Boolean Functions

2019 ◽  
Vol 33 ◽  
pp. 2867-2875 ◽  
Author(s):  
Xuanxiang Huang ◽  
Kehang Fang ◽  
Liangda Fang ◽  
Qingliang Chen ◽  
Zhao-Rong Lai ◽  
...  
Keyword(s):  
Data Structure ◽  
Boolean Functions ◽  
Canonical Representation ◽  
Experimental Results ◽  
Compact Representation ◽  
Decision Diagrams ◽  
Canonical Forms

In this paper, we present a novel data structure for compact representation and effective manipulations of Boolean functions, called Bi-Kronecker Functional Decision Diagrams (BKFDDs). BKFDDs integrate the classical expansions (the Shannon and Davio expansions) and their bi-versions. Thus, BKFDDs are the generalizations of existing decision diagrams: BDDs, FDDs, KFDDs and BBDDs. Interestingly, under certain conditions, it is sufficient to consider the above expansions (the classical expansions and their bi-versions). By imposing reduction and ordering rules, BKFDDs are compact and canonical forms of Boolean functions. The experimental results demonstrate that BKFDDs outperform other existing decision diagrams in terms of sizes.

scholarly journals BDD based construction of resilient functions

2011 ◽  
Vol 24 (3) ◽  
pp. 341-356
Author(s):  
Stanislav Stankovic ◽  
Jaakko Astola
Keyword(s):  
Boolean Functions ◽  
Special Class ◽  
Binary Decision Diagrams ◽  
Compact Representation ◽  
Decision Diagrams ◽  
Binary Decision ◽  
Construction Methods ◽  
Resilient Functions ◽  
Efficient Construction ◽  
High Level

The construction of modern cryptographic systems relies on the so-called resilient Boolean functions, a special class of Boolean functions that possesses a balance between a high level of nonlinearity and correlation immunity. In this paper, we discuss the problem of the compact representation and efficient construction of resilient functions. Binary Decision Diagrams (BDDs) were extensively used as a method of compact representation of various classes of Boolean functions. Furthermore, BDDs offer an opportunity for the efficient implementation of different construction methods for resilient functions. In this paper, we make use of BDDs with attributed edges to provide an implementation of two construction methods proposed by Maitra and Sakar. In addition, we demonstrate that the size of BDDs of resilient functions obtained in this way grows linearly with the number of variables.

scholarly journals Building free Binary Decision Diagrams using SAT solvers

2007 ◽  
Vol 20 (3) ◽  
pp. 381-394 ◽  
Author(s):  
Robert Wille ◽  
Görschwin Fey ◽  
Rolf Drechsler
Keyword(s):  
Boolean Functions ◽  
Binary Decision Diagrams ◽  
Compact Representation ◽  
Decision Diagrams ◽  
Ordered Binary Decision Diagrams ◽  
Binary Decision ◽  
Sat Solvers ◽  
Free Binary Decision Diagrams ◽  
Sat Solver ◽  
Open Question

Free Binary Decision Diagrams (FBDDs) are a data structure for the representation of Boolean functions. In contrast to Ordered Binary Decision Diagrams (OBDDs) FBDDs allow different variable orderings along each path. Thus, FBDDs are the more compact representation while most of the properties of OBDDs are kept. However, how to efficiently build small FBDDs for a given function is still an open question. In this work we propose FBDD construction with the help of SAT solvers. "Recording" the single steps of a SAT solver during the search process leads to an FBDD. Furthermore, by exploiting approaches for identifying isomorphic sub-graphs, i.e. cutlines or cutsets reduced FBDDs are constructed.

AISI 1030

Alloy Digest ◽  
1983 ◽  
Vol 32 (5) ◽  
Keyword(s):  
Fracture Toughness ◽  
Corrosion Resistance ◽  
Low Cost ◽  
Heat Treating ◽  
Plain Carbon Steel ◽  
General Purpose ◽  
Fine Grain ◽  
Steel Mills ◽  
Medium Strength ◽  
Hot Rolled

Abstract AISI 1030 is a plain carbon steel containing nominally 0.30% carbon. It is used in the hot-rolled, normalized, oil-quenched-and-tempered or water-quenched-and-tempered conditions for general-purpose engineering and construction. It provides medium strength and toughness at low cost. Among its many uses are axles, bolts, gears and building sections. All data are on a single heat of fine-grain steel. This datasheet provides information on composition, physical properties, hardness, elasticity, and tensile properties as well as fracture toughness. It also includes information on corrosion resistance as well as forming, heat treating, machining, joining, and surface treatment. Filing Code: CS-94. Producer or source: Carbon and alloy steel mills.

Thermal-aware Output Polarity Selection Based on And-Inverter Graph Manipulation

2019 ◽  
Vol 12 (1) ◽  
pp. 30-39 ◽  
Author(s):  
Apangshu Das ◽  
Sambhu Nath Pradhan
Keyword(s):  
Integrated Circuits ◽  
Power Density ◽  
Logic Synthesis ◽  
Programmable Logic Arrays ◽  
Power Switching ◽  
Nsga Ii ◽  
Multi Level ◽  
Search Approach ◽  
Efficient Power ◽  
The Impact

Background: Output polarity of the sub-function is generally considered to reduce the area and power of a circuit at the two-level realization. Along with area and power, the power-density is also one of the significant parameter which needs to be consider, because power-density directly converges to circuit temperature. More than 50% of the modern day integrated circuits are damaged due to excessive overheating. Methods: This work demonstrates the impact of efficient power density based logic synthesis (in the form of suitable polarity selection of sub-function of Programmable Logic Arrays (PLAs) for its multilevel realization) for the reduction of temperature. Two-level PLA optimization using output polarity selection is considered first and compared with other existing techniques and then And-Invert Graphs (AIG) based multi-level realization has been considered to overcome the redundant solution generated in two-level synthesis. AIG nodes and associated power dissipation can be reduced by rewriting, refactoring and balancing technique. Reduction of nodes leads to the reduction of the area but on the contrary increases power and power density of the circuit. A meta-heuristic search approach i.e., Nondominated Sorting Genetic Algorithm-II (NSGA-II) is proposed to select the suitable output polarity of PLA sub-functions for its optimal realization. Results: Best power density based solution saves up to 8.29% power density compared to ‘espresso – dopo’ based solutions. Around 9.57% saving in area and 9.67% saving in power (switching activity) are obtained with respect to ‘espresso’ based solution using NSGA-II. Conclusion: Suitable output polarity realized circuit is converted into multi-level AIG structure and synthesized to overcome the redundant solution at the two-level circuit. It is observed that with the increase in power density, the temperature of a particular circuit is also increases.

scholarly journals A Novel Graphical Technique for Combinational Logic Representation and Optimization

Complexity ◽  
2017 ◽  
Vol 2017 ◽  
pp. 1-12
Author(s):  
Vedhas Pandit ◽  
Björn Schuller
Keyword(s):  
Boolean Functions ◽  
Discrete Systems ◽  
Boolean Logic ◽  
Decision Diagrams ◽  
New Paradigm ◽  
Binary Decision ◽  
Graphical Technique ◽  
A New Technique ◽  
Logic Functions ◽  
Logical Functions

We present a new technique for defining, analysing, and simplifying digital functions, through hand-calculations, easily demonstrable therefore in the classrooms. It can be extended to represent discrete systems beyond the Boolean logic. The method is graphical in nature and provides complete ‘‘implementation-free” description of the logical functions, similar to binary decision diagrams (BDDs) and Karnaugh-maps (K-maps). Transforming a function into the proposed representations (also the inverse) is a very intuitive process, easy enough that a person can hand-calculate these transformations. The algorithmic nature allows for its computing-based implementations. Because the proposed technique effectively transforms a function into a scatter plot, it is possible to represent multiple functions simultaneously. Usability of the method, therefore, is constrained neither by the number of inputs of the function nor by its outputs in theory. This, being a new paradigm, offers a lot of scope for further research. Here, we put forward a few of the strategies invented so far for using the proposed representation for simplifying the logic functions. Finally, we present extensions of the method: one that extends its applicability to multivalued discrete systems beyond Boolean functions and the other that represents the variants in terms of the coordinate system in use.

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