scholarly journals Impact of the Stress on the Sub-Micron N-Metal Oxide Semiconductor Field Effect Transistor Characteristics

2001 ◽  
Vol 24 (3) ◽  
pp. 187-199 ◽  
Author(s):  
R. Marrakh ◽  
A. Bouhdada
Keyword(s):  
Field Effect Transistor ◽  
Current Model ◽  
Drain Current ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Short Channel ◽  
Interface Charge ◽  
Effect Transistor ◽  
Spatio Temporal ◽  
The Impact

In this paper, we present a drain current model for stressed short-channel MOSFET's. Stress conditions are chosen so that the interface states generated by hot-carriers are dominant. The defects generated during stress time are simulated by a spatio-temporal gaussian distribution. The parasitic source and drain resistances are included. We also investigate the impact of the interface charge density, generated during stress, on the transconductance. Simulation results show a significant degradation of the drain current versus stress time.

Effect of Metal - Silicon Nanowire Contacts on the Performance of Accumulation Metal Oxide Semiconductor Field Effect Transistor

2008 ◽  
Vol 1144 ◽  
Author(s):  
Pranav Garg ◽  
Yi Hong ◽  
Md. Mash-Hud Iqbal ◽  
Stephen J. Fonash
Keyword(s):  
Metal Oxide ◽  
Silicon Nanowires ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Silicon Nanowire ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Manufacturing Cost ◽  
Effect Transistor ◽  
The Impact

ABSTRACTRecently, we have experimentally demonstrated a very simply structured unipolar accumulation-type metal oxide semiconductor field effect transistor (AMOSFET) using grow-in-place silicon nanowires. The AMOSFET consists of a single doping type nanowire, metal source and drain contacts which are separated by a partially gated region. Despite its simple configuration, it is capable of high performance thereby offering the potential of a low manufacturing-cost transistor. Since the quality of the metal/semiconductor ohmic source and drain contacts impacts AMOSFET performance, we repot here on initial exploration of contact variations and of the impact of thermal process history. With process optimization, current on/off ratios of 106 and subthreshold swings of 70 mV/dec have been achieved with these simple devices

Performance Evaluation of Silicon-Transition Metal Dichalcogenides Heterostructure Based Steep Subthreshold Slope-Field Effect Transistor Using Non-Equilibrium Green’s Function

2020 ◽  
Vol 18 (6) ◽  
pp. 468-476
Author(s):  
Prateek Kumar ◽  
Maneesha Gupta ◽  
Naveen Kumar ◽  
Marlon D. Cruz ◽  
Hemant Singh ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Molybdenum Disulphide ◽  
Short Channel ◽  
Tungsten Disulphide ◽  
Channel Effects ◽  
Effect Transistor

With technology invading nanometer regime performance of the Metal-Oxide-semiconductor Field Effect Transistor is largely hampered by short channel effects. Most of the simulation tools available do not include short channel effects and quantum effects in the analysis which raises doubt on their authenticity. Although researchers have tried to provide an alternative in the form of tunnel field-effect transistors, junction-less transistors, etc. but they all suffer from their own set of problems. Therefore, Metal-Oxide-Semiconductor Field-Effect Transistor remains the backbone of the VLSI industry. This work is dedicated to the design and study of the novel tub-type Metal-Oxide-Semiconductor Field-Effect Transistor. For simulation Non-Equilibrium Green’s Function is used as the primary model of simulation. The device is analyzed under different physical variations like work function, permittivity, and interface trap charge. This work uses Silicon-Molybdenum Disulphide heterojunction and Silicon-Tungsten Disulphide heterojunction as channel material. Results for both the heterojunctions are compared. It was analyzed that Silicon-Molybdenum Disulphide heterojunction provides better linearity and Silicon-Tungsten Disulphide heterojunction provides better switching speed than conventional Metal-Oxide-Semiconductor Field-Effect Transistor.

Quantum Modelling of Nanoscale Silicon Gate-All-Around Field Effect Transistor

2020 ◽  
Vol 64 ◽  
pp. 115-122
Author(s):  
P. Vimala ◽  
N.R. Nithin Kumar
Keyword(s):  
Analytical Model ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Inversion Layer ◽  
Drain Current ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Effect Transistor ◽  
Quantum Mechanical Effects ◽  
Novel Devices

The paper introduces an analytical model for gate all around (GAA) or Surrounding Gate Metal Oxide Semiconductor Field Effect Transistor (SG-MOSFET) inclusive of quantum mechanical effects. The classical oxide capacitance is replaced by the capacitance incorporating quantum effects by including the centroid parameter. The quantum variant of inversion charge distribution function, inversion layer capacitance, drain current, and transconductance expressions are modeled by employing this model. The established analytical model results agree with the simulated results, verifying these models' validity and providing theoretical supports for designing and applying these novel devices.

scholarly journals Subthreshold Characteristics of a Metal-Oxide–Semiconductor Field-Effect Transistor with External PVDF Gate Capacitance

Crystals ◽  
2019 ◽  
Vol 9 (12) ◽  
pp. 673
Author(s):  
Jing-Jenn Lin ◽  
Ji-Hua Tao ◽  
You-Lin Wu
Keyword(s):  
Metal Oxide ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Drain Current ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Subthreshold Slope ◽  
Ferroelectric Capacitor ◽  
In Series ◽  
Effect Transistor

An organic ferroelectric capacitor, using polyvinylidene difluoride (PVDF) as the dielectric, was fabricated. By connecting the PVDF capacitor in series to the gate of a commercially purchased metal-oxide–semiconductor field-effect transistor (MOSFET), drain current (ID)–drain voltage (VD) characteristics and drain current (ID)–gate voltage (VG) characteristics were measured. In addition, the subthreshold slopes of the MOSFET were determined from the ID–VG curves. It was found that the subthreshold slope could be effectively reduced by 23% of its original value when the PVDF capacitor was added to the gate of the MOSFET.

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