scholarly journals Layout Aware Optimization of High Speed Fixed Coefficient FIR Filters for FPGAs

2010 ◽  
Vol 2010 ◽  
pp. 1-17 ◽  
Author(s):  
Shahnam Mirzaei ◽  
Ryan Kastner ◽  
Anup Hosangadi
Keyword(s):  
High Speed ◽  
Finite Impulse Response ◽  
Fir Filters ◽  
Second Phase ◽  
Distributed Arithmetic ◽  
Gate Arrays ◽  
Length Estimation ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Coefficient Multipliers

We present a method for implementing high speed finite impulse response (FIR) filters on field programmable gate arrays (FPGAs). Our algorithm is a multiplierless technique where fixed coefficient multipliers are replaced with a series of add and shift operations. The first phase of our algorithm uses registered adders and hardwired shifts. Here, a modified common subexpression elimination (CSE) algorithm reduces the number of adders while maintaining performance. The second phase optimizes routing delay using prelayout wire length estimation techniques to improve the final placed and routed design. The optimization target platforms are Xilinx Virtex FPGA devices where we compare the implementation results with those produced by Xilinx Coregen, which is based on distributed arithmetic (DA). We observed up to 50% reduction in the number of slices and up to 75% reduction in the number of look up tables (LUTs) for fully parallel implementations compared to DA method. Also, there is 50% reduction in the total dynamic power consumption of the filters. Our designs perform up to 27% faster than the multiply accumulate (MAC) filters implemented by Xilinx Coregen tool using DSP blocks. For placement, there is a saving up to 20% in number of routing channels. This results in lower congestion and up to 8% reduction in average wirelength.

High Speed Implementation of a SHA-3 Core on Virtex-5 and Virtex-6 FPGAs

2016 ◽  
Vol 25 (07) ◽  
pp. 1650069 ◽  
Author(s):  
Muzaffar Rao ◽  
Thomas Newe ◽  
Ian Grout ◽  
Avijit Mathur
Keyword(s):  
High Speed ◽  
Second Phase ◽  
Two Phase ◽  
Gate Arrays ◽  
Implementation Approach ◽  
Hash Algorithm ◽  
Core Function ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Secure Hash Algorithm

This work presents a novel technique for a high-speed implementation of the newly selected cryptographic hash function, Secure Hash Algorithm-3 (SHA-3) on Xilinx’s Virtex-5 and Virtex-6 Field Programmable Gate Arrays (FPGAs). The proposed technique consists of a two-phase implementation approach. In the first phase, all steps of the SHA-3 core are logically combined, which helps to eliminate the intermediate states of core function, these states utilize more area and also slow the execution. The second phase deals with the hardware implementation of the first phase equations using Xilinx Look-Up-Table (LUT) primitives. This two phase implementation technique results in a throughput of 19.241[Formula: see text]Gbps on a Virtex-6 FPGA; this is the highest reported throughput to date for an FPGA implementation of SHA-3. This high throughput makes this technique ideally suited for the provision of Bump In The Wire (BITW) security for Internet of Things (IoT) applications.

scholarly journals BPR-TCAM—Block and Partial Reconfiguration based TCAM on Xilinx FPGAs

Electronics ◽  
2020 ◽  
Vol 9 (2) ◽  
pp. 353 ◽  
Author(s):  
Anees Ullah ◽  
Ali Zahir ◽  
Noaman A. Khan ◽  
Waleed Ahmad ◽  
Alexis Ramos ◽  
...  
Keyword(s):  
Resource Utilization ◽  
High Speed ◽  
State Of The Art ◽  
Field Programmable Gate Arrays ◽  
Partial Reconfiguration ◽  
Gate Arrays ◽  
Content Addressable Memories ◽  
Field Programmable ◽  
Programmable Gate Arrays

Field Programmable Gate Arrays (FPGAs) based Ternary Content Addressable Memories (TCAMs) are widely used in high-speed networking applications.However, TCAMs are not present on state-of-the-art FPGAs and need to be emulated on SRAM-based memories (i.e., LUTRAMs and Block RAMs) which requires a large amount of FPGA resources. In this paper, we present an efficient methodology to implement FPGA-based TCAMs with significant resource savings compared to existing schemes. The proposed methodology exploits the fracturable nature of Look Up Tables (LUTs) and the built-in slice carry-chains for simultaneous mapping of two rules and its matching logic to a single FPGA slice. Multiple slices can be stacked together to build deeper and wider TCAMs in a modular way. The combination of all these techniques results in significant savings in resource utilization compared to existing approaches.

scholarly journals IMAGE FILTERING WITH FIELD PROGRAMMABLE GATE ARRAY / VAIZDŲ FILTRAVIMAS LAUKU PROGRAMUOJAMA LOGINE MATRICA

2013 ◽  
Vol 5 (2) ◽  
pp. 70-73
Author(s):  
Arūnas Šlenderis ◽  
Gintautas Daunys
Keyword(s):  
Finite Impulse Response ◽  
Image Filtering ◽  
C Language ◽  
Nios Ii ◽  
Finite Impulse Response Filters ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Hardware Description ◽  
Impulse Response Filters

The research examined the use of field programmable gate arrays (FPGA) in image filtering. Experimental and theoretical researches were reviewed. Experiments with Cyclone III family FPGA chip with implemented NIOS II soft processor were considered. Image filtering was achieved with symmetrical and asymmetrical finite impulse response filters with convolution kernel. The system, which was implemented with 3×3 symmetrical filter, which was implemented using the hardware description language, uses 59% of logic elements of the chip and 10 multiplication elements. The system with asymmetrical filter uses the same amount of logic elements and 13 multiplication elements. Both filter systems consume approx. 545 mW of power. The system, which is designed for filter implementation in C language, uses 65% of all logical elements and consumes 729 mW of power. Article in Lithuanian. Santrauka Nagrinėjama, kaip vaizdams filtruoti naudojamos lauku programuojamos loginės matricos (LPLM). Apžvelgti eksperimentiniai ir teoriniai darbai. Atlikti bandymai su Cyclone III šeimos LPLM lustu, kuriame buvo įdiegtas įkeliamasis NIOS II procesorius. Vaizdai filtruoti su simetriniu ir nesimetriniu ribotos impulsinės reakcijos filtrais, naudojant sąsūkos branduolį. Sistema, kuri buvo įdiegta kartu su 3×3 simetriniu filtru, naudojant aparatinės įrangos aprašymo kalbą, naudoja 59 % lusto loginių elementų ir 10 dauginimo elementų. Ši sistema su nesimetriniu filtru naudoja tiek pat loginių elementų ir 13 dauginimo elementų. Abiejų filtrų sistemų naudojama galia yra panaši – apie 545 mW. Sistemos su įkeliamuoju procesoriumi naudojamų loginių elementų dalis siekia 65 %, naudojama galia – 729 mW.

scholarly journals A Comparison of Filtering Approaches Using Low-Speed DACs for Hardware-in-the-Loop Implemented in FPGAs

Electronics ◽  
2019 ◽  
Vol 8 (10) ◽  
pp. 1116 ◽  
Author(s):  
Yushkova ◽  
Sanchez ◽  
de Castro ◽  
Martínez-García
Keyword(s):  
High Speed ◽  
Hardware In The Loop ◽  
Low Speed ◽  
Digital To Analog Converters ◽  
Gate Arrays ◽  
Simulation Techniques ◽  
Input Signals ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Input Waveform

The use of Hardware-in-the-Loop (HIL) systems implemented in Field Programmable Gate Arrays (FPGAs) is constantly increasing because of its advantages compared to traditional simulation techniques. This increase in usage has caused new challenges related to the improvement of their performance and features like the number of output channels, while the price of HIL systems is diminishing. At present, the use of low-speed Digital-to-Analog Converters (DACs) is starting to be a commercial possibility because of two reasons. One is their lower price and the other is their lower pin count, which determines the number and price of the FPGAs that are necessary to handle those DACs. This paper compares four filtering approaches for providing suitable data to low-speed DACs, which help to filter high-speed input signals, discarding the need of using expensive high-speed DACS, and therefore decreasing the total cost of HIL implementations. Results show that the selection of the appropriate filter should be based on the type of the input waveform and the relative importance of the dynamics versus the area.

FPGA TECHNOLOGY IN PROCESS TOMOGRAPHY

2016 ◽  
Vol 78 (7-4) ◽  
Author(s):  
Lean Thiam Siow ◽  
Mohd Hafiz Fazalul Rahiman ◽  
Ruzairi Abdul Rahim ◽  
Mohd Shukry Abdul Majid ◽  
Salman Sayyidi Hamzah ◽  
...  
Keyword(s):  
High Speed ◽  
Low Cost ◽  
Gate Arrays ◽  
Tomography System ◽  
Process Tomography ◽  
Ultrasonic Process ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Future Work

The aims of this paper are to provide a review of the process tomography applications employing field programmable gate arrays (FPGA) and to understand current FPGA related researches, in order to seek for the possibility to applied FPGA technology in an ultrasonic process tomography system. FPGA allows users to implement complete systems on a programmable chip, meanwhile, five main benefits of applying the FPGA technology are performance, time to market, cost, reliability, and long-term maintenance. These advantages definitely could help in the revolution of process tomography, especially for ultrasonic process tomography and electrical process tomography. Future work is focused on the ultrasonic process tomography for chemical process column investigation using FPGA for the aspects of low cost, high speed and reconstructed image quality.

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