FPGA TECHNOLOGY IN PROCESS TOMOGRAPHY

The aims of this paper are to provide a review of the process tomography applications employing field programmable gate arrays (FPGA) and to understand current FPGA related researches, in order to seek for the possibility to applied FPGA technology in an ultrasonic process tomography system. FPGA allows users to implement complete systems on a programmable chip, meanwhile, five main benefits of applying the FPGA technology are performance, time to market, cost, reliability, and long-term maintenance. These advantages definitely could help in the revolution of process tomography, especially for ultrasonic process tomography and electrical process tomography. Future work is focused on the ultrasonic process tomography for chemical process column investigation using FPGA for the aspects of low cost, high speed and reconstructed image quality.

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Evaluation of the Different Numerical Formats for HIL Models of Power Converters after the Adoption of VHDL-2008 by Xilinx

Electronics ◽

10.3390/electronics10161952 ◽

2021 ◽

Vol 10 (16) ◽

pp. 1952

Author(s):

Eva M. Cirugeda-Roldán ◽

María Sofía Martínez-García ◽

Alberto Sanchez ◽

Angel de Castro

Keyword(s):

High Speed ◽

Power Converters ◽

Low Cost ◽

Hardware In The Loop ◽

Main Design ◽

Gate Arrays ◽

The World ◽

Field Programmable ◽

Programmable Gate Arrays ◽

Area Optimization

Hardware in the loop is a widely used technique in power electronics, allowing to test and debug in real time (RT) at a low cost. In this context, field-programmable gate arrays (FPGAs) play an important role due to the high-speed requirements of RT simulations, in which area optimization is also crucial. Both characteristics, area and speed, are affected by the numerical formats (NFs) and their rounding modes. Regarding FPGAs, Xilinx is one of the largest manufacturers in the world, offering Vivado as its main design suite, but it was not until the release of Vivado 2020.2 that support for the IEEE NF libraries of VHDL-2008 was included. This work presents an exhaustive evaluation of the performance of Vivado 2020.2 in terms of area and speed using the native IEEE libraries of VHDL-2008 regarding NF. Results show that even though fixed-point NFs optimize area and speed, if a user prefers the use of floating-point NFs, with this new release, it can be synthesized—which could not be done in previous versions of Vivado. Although support for the native IEEE libraries of VHDL-2008 was included in Vivado 2020.2, it still lacks some issues regarding NF conversion during synthesis while support for simulation is not yet included.

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High Performance Low Cost Implementation of FPGA-Based Fractional-Order Operators

Volume 6: 5th International Conference on Multibody Systems, Nonlinear Dynamics, and Control, Parts A, B, and C ◽

10.1115/detc2005-84796 ◽

2005 ◽

Cited By ~ 3

Author(s):

Cindy X. Jiang ◽

Tom T. Hartley ◽

Joan E. Carletta

Keyword(s):

Fractional Order ◽

Word Length ◽

High Performance ◽

Low Cost ◽

Careful Consideration ◽

Order System ◽

System Quality ◽

Gate Arrays ◽

Field Programmable ◽

Programmable Gate Arrays

Hardware implementation of fractional-order differentiators and integrators requires careful consideration of issues of system quality, hardware cost, and speed. This paper proposes using field programmable gate arrays (FPGAs) to implement fractional-order systems, and demonstrates the advantages that FPGAs provide. As an illustration, the fundamental operators to a real power is approximated via the binomial expansion of the backward difference. The resulting high-order FIR filter is implemented in a pipelined multiplierless architecture on a low-cost Spartan-3 FPGA. Unlike common digital implementations in which all filter coefficients have the same word length, this approach exploits variable word length for each coefficient. Our system requires twenty percent less hardware than a system of comparable quality generated by Xilinx’s System Generator on its most area-efficient multiplierless setting. The work shows an effective way to implement a high quality, high throughput approximation to a fractional-order system, while maintaining less cost than traditional FPGA-based designs.

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Long term storage reliability of antifuse field programmable gate arrays

Microelectronics Reliability ◽

10.1016/j.microrel.2013.06.016 ◽

2013 ◽

Vol 53 (12) ◽

pp. 2052-2056 ◽

Cited By ~ 9

Author(s):

Nishad Patil ◽

Diganta Das ◽

Estelle Scanff ◽

Michael Pecht

Keyword(s):

Field Programmable Gate Arrays ◽

Gate Arrays ◽

Long Term Storage ◽

Field Programmable ◽

Programmable Gate Arrays ◽

Term Storage

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A Primer for Telemetry Interfacing in Accordance with NASA Standards Using Low Cost FPGAs

Journal of Astronomical Instrumentation ◽

10.1142/s225117171640002x ◽

2016 ◽

Vol 05 (01) ◽

pp. 1640002

Author(s):

Jake McCoy ◽

Ted Schultz ◽

James Tutt ◽

Thomas Rogers ◽

Drew Miles ◽

...

Keyword(s):

High Speed ◽

Low Cost ◽

Photon Counting ◽

Sounding Rocket ◽

Photon Counting Detector ◽

Field Programmable ◽

Programmable Gate Arrays ◽

Custom Hardware ◽

Commercial Off The Shelf ◽

Main Component

Photon counting detector systems on sounding rocket payloads often require interfacing asynchronous outputs with a synchronously clocked telemetry (TM) stream. Though this can be handled with an on-board computer, there are several low cost alternatives including custom hardware, microcontrollers and field-programmable gate arrays (FPGAs). This paper outlines how a TM interface (TMIF) for detectors on a sounding rocket with asynchronous parallel digital output can be implemented using low cost FPGAs and minimal custom hardware. Low power consumption and high speed FPGAs are available as commercial off-the-shelf (COTS) products and can be used to develop the main component of the TMIF. Then, only a small amount of additional hardware is required for signal buffering and level translating. This paper also discusses how this system can be tested with a simulated TM chain in the small laboratory setting using FPGAs and COTS specialized data acquisition products.

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BPR-TCAM—Block and Partial Reconfiguration based TCAM on Xilinx FPGAs

Electronics ◽

10.3390/electronics9020353 ◽

2020 ◽

Vol 9 (2) ◽

pp. 353 ◽

Cited By ~ 1

Author(s):

Anees Ullah ◽

Ali Zahir ◽

Noaman A. Khan ◽

Waleed Ahmad ◽

Alexis Ramos ◽

...

Keyword(s):

Resource Utilization ◽

High Speed ◽

State Of The Art ◽

Field Programmable Gate Arrays ◽

Partial Reconfiguration ◽

Gate Arrays ◽

Content Addressable Memories ◽

Field Programmable ◽

Programmable Gate Arrays

Field Programmable Gate Arrays (FPGAs) based Ternary Content Addressable Memories (TCAMs) are widely used in high-speed networking applications.However, TCAMs are not present on state-of-the-art FPGAs and need to be emulated on SRAM-based memories (i.e., LUTRAMs and Block RAMs) which requires a large amount of FPGA resources. In this paper, we present an efficient methodology to implement FPGA-based TCAMs with significant resource savings compared to existing schemes. The proposed methodology exploits the fracturable nature of Look Up Tables (LUTs) and the built-in slice carry-chains for simultaneous mapping of two rules and its matching logic to a single FPGA slice. Multiple slices can be stacked together to build deeper and wider TCAMs in a modular way. The combination of all these techniques results in significant savings in resource utilization compared to existing approaches.

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A low-cost remote laboratory of field programmable gate arrays

Proceedings of 2015 12th International Conference on Remote Engineering and Virtual Instrumentation (REV) ◽

10.1109/rev.2015.7087286 ◽

2015 ◽

Cited By ~ 1

Author(s):

Huy Nguyen Quang ◽

Thang Manh Hoang

Keyword(s):

Low Cost ◽

Field Programmable Gate Arrays ◽

Remote Laboratory ◽

Gate Arrays ◽

Field Programmable ◽

Programmable Gate Arrays

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Nonvolatile Nanoelectromechanical Memory Switches for Low-Power and High-Speed Field-Programmable Gate Arrays

IEEE Transactions on Electron Devices ◽

10.1109/ted.2014.2380992 ◽

2015 ◽

Vol 62 (2) ◽

pp. 673-679 ◽

Cited By ~ 14

Author(s):

Yong Jun Kim ◽

Woo Young Choi

Keyword(s):

Low Power ◽

High Speed ◽

Field Programmable Gate Arrays ◽

Gate Arrays ◽

Field Programmable ◽

Programmable Gate Arrays

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A High Resolution Vernier Digital-to-Time Converter Implemented with 65 nm FPGA

Applied Sciences ◽

10.3390/app9132705 ◽

2019 ◽

Vol 9 (13) ◽

pp. 2705

Author(s):

Chenggang Yan ◽

Chen Hu ◽

Jianhui Wu

Keyword(s):

High Resolution ◽

Low Cost ◽

Phase Locked Loops ◽

Least Significant Bit ◽

Gate Arrays ◽

Differential Nonlinearity ◽

Field Programmable ◽

Programmable Gate Arrays ◽

Fpga Chip ◽

Fine Resolution

In this paper, a digital-to-time converter (DTC) based on the three delay lines (3D) Vernier principle is proposed and implemented with field programmable gate arrays (FPGAs). Based on the 3D Vernier principle, the DTC is realized by three period approximate phase locked loops (PLLs). The theoretical fine resolution of the proposed DTC is improved by calculating the period difference two times. The achieved resolution of the proposed DTC is 203 fs realized with an Altera Stratix III FPGA chip, which is about tenfold higher than traditional FPGA-DTC implemented with the same series FPGAs. The worst absolute differential nonlinearity (DNL) and integral nonlinearity (INL) are verified smaller than 0.88 least significant bit (LSB) and 4.4 LSB, respectively. By optimized computation logic, there are only 448 adaptive look-up-tables (ALUTs), 237 registers and three phase locked loops (PLLs) utilized for circuit implementation. Experimental results prove that the proposed DTC features high resolution with low cost.

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A Comparison of Filtering Approaches Using Low-Speed DACs for Hardware-in-the-Loop Implemented in FPGAs

Electronics ◽

10.3390/electronics8101116 ◽

2019 ◽

Vol 8 (10) ◽

pp. 1116 ◽

Cited By ~ 4

Author(s):

Yushkova ◽

Sanchez ◽

de Castro ◽

Martínez-García

Keyword(s):

High Speed ◽

Hardware In The Loop ◽

Low Speed ◽

Digital To Analog Converters ◽

Gate Arrays ◽

Simulation Techniques ◽

Input Signals ◽

Field Programmable ◽

Programmable Gate Arrays ◽

Input Waveform

The use of Hardware-in-the-Loop (HIL) systems implemented in Field Programmable Gate Arrays (FPGAs) is constantly increasing because of its advantages compared to traditional simulation techniques. This increase in usage has caused new challenges related to the improvement of their performance and features like the number of output channels, while the price of HIL systems is diminishing. At present, the use of low-speed Digital-to-Analog Converters (DACs) is starting to be a commercial possibility because of two reasons. One is their lower price and the other is their lower pin count, which determines the number and price of the FPGAs that are necessary to handle those DACs. This paper compares four filtering approaches for providing suitable data to low-speed DACs, which help to filter high-speed input signals, discarding the need of using expensive high-speed DACS, and therefore decreasing the total cost of HIL implementations. Results show that the selection of the appropriate filter should be based on the type of the input waveform and the relative importance of the dynamics versus the area.

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