scholarly journals A New 7-Level Symmetric Multilevel Inverter with Minimum Number of Switches

2013 ◽  
Vol 2013 ◽  
pp. 1-8 ◽  
Author(s):  
S. Umashankar ◽  
T. S. Sreedevi ◽  
V. G. Nithya ◽  
D. Vijayakumar

Though the multilevel inverters hold attractive features, usage of more switches in the conventional configuration poses a limitation to its wide range application. Therefore, a renewed 7-level multilevel inverter topology is introduced incorporating the least number of unidirectional switches and gate trigger circuitry, thereby ensuring the minimum switching losses, reducing size and installation cost. The new topology is well suited for drives and renewable energy applications. The performance quality in terms of THD and switching losses of the new MLI is compared with conventional cascaded MLI and other existing 7-level reduced switch topologies using carrier-based PWM techniques. The results are validated using MATLAB/SIMULINK.

2017 ◽  
Vol 7 (1.5) ◽  
pp. 209
Author(s):  
B.Vijaya Krishna ◽  
B. Venkata Prashanth ◽  
P. Sujatha

Multilevel Inverters (MLI) have very good features when compared to Inverters. But using more switches in the conventional configuration will reduce its application in a wider range. For that reason a modified 7-level MLI Topology is presented. This new topology consists of less number of switches that can be reduced to the maximum extent and a separate gate trigger circuit. This will reduce the switching losses, reduce the size of the multilevel inverter, and cost of installation. This new topology can be used in Electrical drives and renewable energy applications. Performance of the new MLI is tested via. Total harmonic distortion. This construction structure of this multilevel inverter topology can also be increased for 9-level, 11-level and so on and simulated by the use of MATLAB/SIMULINK. A separate Carrier Based PWM Technique is used for the pulse generation in this configuration.


Multilevel inverters produced lot of interest in academia and industry as they are becoming feasible technology for number of applications. These are considered as the progressing power converter topologies. To generate a quality output waveform with minimum number of switches, reduced switch multilevel inverter topologies has come in focus. This paper introduces a modified symmetrical MLI with reduced component count thereby ensuring the minimum switching losses, reduced total harmonic distortion, Size and installation cost. By proper combination of switches it produces a staircase output waveform with low harmonic distortion. In this paper novel symmetrical inverter topology with reduced component count based on level shift phase opposition and disposition PWM (PODPWM) is proposed. The results are validated using MATLAB/SIMULINK.


Author(s):  
Ujwala Gajula Et.al

Multilevel inverters (MLIs) have been extensively used and gained interest over last few decades in industrial and grid connected renewable energy applications because of its numerous merits. Besides various advantages like obtaining reduced harmonic distortion and lesser dv/dt stress across switches it has the capability of generating any number of levels. The theory of multilevel concept was initiated for high power and high/medium voltage applications as they are helpful in interfacing with renewable energy sources. By proper combination of the switches it generates a stair case output with reduced harmonic distortion because of this MLI is widely used and it became one of the advanced power converter topology. The rise of new topologies has attained importance over conventional multilevel inverter topologies, which generates more number of levels with reduced switch components. This paper presents various conventional MLI topologies and hybrid MLI topologies for renewable energy applications. Also, this review paper includes different modulation strategies which plays an important role to improve the overall performance of MLI.


2022 ◽  
Vol 18 (1) ◽  
pp. 48-57
Author(s):  
Aws Al-Jrew ◽  
Jawad Mahmood ◽  
Ramzy Ali

In this article, a comparison of innovative multilevel inverter topology with standard topologies has been conducted. The proposed single phase five level inverter topology has been used for induction heating system. This suggested design generates five voltage levels with a fewer number of power switches. This reduction in number of switches decreases the switching losses and the number of driving circuits and reduce the complexity of control circuit. It also reduces the cost and size for the filter used. Analysis and comparison has been done among the conventional topologies (neutral clamped and cascade H-bridge multilevel inverters) with the proposed inverter topology. The analysis includes the total harmonic distortion THD, efficiency and overall performance of the inverter systems. The simulation and analysis have been done using MATLAB/ SIMULINK. The results show good performance for the proposed topology in comparison with the conventional topologies.


2018 ◽  
Vol 69 (3) ◽  
pp. 233-238
Author(s):  
Cajethan M. Nwosu ◽  
Cosmas U. Ogbuka ◽  
Stephen E. Oti

Abstract An analysis, design and simulation of digital controlled symmetrical seven levels inverter is presented in this paper. Against the contemporary use of two asymmetrical DC sources with two H-bridge cells to generate seven levels inverter two DC sources of equal voltage ratings are used through digital control strategy to realize seven levels output voltage. By utilizing limited number of active switching components and avoiding the usual complex PWM control techniques for multilevel inverters by way of digital control strategy, high efficiency multilevel inverter systems due to reduction in total harmonic distortion and switching losses is guaranteed. Owing to symmetry of the H-bridge cells, a simple and single programmed counter built around J-K flip is required irrespective of number of cascades. The analyzed and designed system has been simulated in MATLAB/SIMULINK environment. With an R-L load of 200 Ω and 200 mH, improved total harmonic distortions (THDs) for the inverter current and voltage are 7.59% and 16.89% respectively. The obtained results show that the control-circuit-based multilevel inverter topology is most suited for applications in solar powered inverter systems.


2019 ◽  
Vol 8 (2) ◽  
pp. 1230-1233

The Multilevel inverters are known for their high power capability and reliability. They produce the output in the form of staircase waveform. If the number of level increases then almost perfect sine wave can be attained at the output. The increase in number of levels improves the power quality but it also increases the complexity in control and cost, which will increase the switching losses also. Hence there is a need for research in the multilevel inverter topology to have reduced number of switches for increased levels than the conventional and pre-proposed topologies. The purpose of this paper is to design the new topology on multilevel inverter with reduced switching devices


Author(s):  
Ali Seifi ◽  
Majid Hosseinpour ◽  
Abdolmajid Dejamkhooy

Multilevel inverters are a new generation of DC–AC converters at medium and high voltage and power levels. In this paper, a new single-phase cascaded multilevel inverter is presented. For this purpose, a new basic cell is presented at first. Then, the new multilevel inverter structure is yielded by series connection of these cells. The proposed new cell is only capable of generating positive voltage levels, and therefore, to produce zero and negative voltage levels, the proposed structure is constructed based on H-bridge module. In order to reduce the maximum blocking voltage especially on H-bridge switches, the cascaded connection of the proposed converter is investigated. A comprehensive comparison is carried out between the proposed multilevel inverter with the classical and recently introduced structures in terms of the number of switching devices, the number of drivers, the total blocking voltage of the switches as well as the loss and efficiency. The accuracy of the proposed inverter’s performance is simulated in MATLAB/Simulink in symmetric and asymmetric topologies for a 17-level and 23-level output voltage respectively, and then evaluated by the laboratory prototype.


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