A switch-source cell-based cascaded multilevel inverter topology with minimum number of power electronics components

2020 ◽  
pp. 014233122097413
Author(s):  
Ali Seifi ◽  
Majid Hosseinpour ◽  
Abdolmajid Dejamkhooy
Keyword(s):  
Multilevel Inverter ◽  
Multilevel Inverters ◽  
Blocking Voltage ◽  
Positive Voltage ◽  
Minimum Number ◽  
Comprehensive Comparison ◽  
Ac Converters ◽  
New Generation ◽  
Cascaded Multilevel Inverter ◽  
Inverter Topology

Multilevel inverters are a new generation of DC–AC converters at medium and high voltage and power levels. In this paper, a new single-phase cascaded multilevel inverter is presented. For this purpose, a new basic cell is presented at first. Then, the new multilevel inverter structure is yielded by series connection of these cells. The proposed new cell is only capable of generating positive voltage levels, and therefore, to produce zero and negative voltage levels, the proposed structure is constructed based on H-bridge module. In order to reduce the maximum blocking voltage especially on H-bridge switches, the cascaded connection of the proposed converter is investigated. A comprehensive comparison is carried out between the proposed multilevel inverter with the classical and recently introduced structures in terms of the number of switching devices, the number of drivers, the total blocking voltage of the switches as well as the loss and efficiency. The accuracy of the proposed inverter’s performance is simulated in MATLAB/Simulink in symmetric and asymmetric topologies for a 17-level and 23-level output voltage respectively, and then evaluated by the laboratory prototype.

scholarly journals Switched Capacitor Based Cascaded Half-Bridge Multilevel Inverter With Voltage Boosting Feature

2021 ◽  
Vol 6 (1) ◽  
pp. 63-73
Author(s):  
Hossein Khoun-Jahan ◽  
Keyword(s):  
Multilevel Inverter ◽  
Inrush Current ◽  
Switched Capacitor ◽  
Multilevel Inverters ◽  
Main Drawback ◽  
Front End ◽  
Simulation Results ◽  
Resonant Capacitor ◽  
Cascaded Multilevel Inverter ◽  
Inverter Topology

Cascaded multilevel inverter (CMI) topology is prevalent in many applications. However, the CMI requires many switches and isolated dc sources, which is the main drawback of this type of inverter. As a result, the volume, cost and complexity of the CMI topology are increased and the efficiency is deteriorated. This paper thus proposes a switched-capacitor-based multilevel inverter topology with half-bridge cells and only one dc source. Compared to the conventional CMI, the proposed inverter uses almost half the number of switches, while maintaining a boosting capability. Additionally, the main drawback of switched-capacitor multilevel inverters is the capacitor inrush current. This problem is also averted in the proposed topology by using a charging inductor or quasi-resonant capacitor charging with a front-end boost converter. Simulation results and lab-scale experimental verifications are provided to validate the feasibility and viability of the proposed inverter topology.

scholarly journals A New 7-Level Symmetric Multilevel Inverter with Minimum Number of Switches

2013 ◽  
Vol 2013 ◽  
pp. 1-8 ◽  
Author(s):  
S. Umashankar ◽  
T. S. Sreedevi ◽  
V. G. Nithya ◽  
D. Vijayakumar
Keyword(s):  
Renewable Energy ◽  
Multilevel Inverter ◽  
Multilevel Inverters ◽  
Energy Applications ◽  
Switching Losses ◽  
Performance Quality ◽  
Wide Range ◽  
Minimum Number ◽  
Inverter Topology ◽  
Installation Cost

Though the multilevel inverters hold attractive features, usage of more switches in the conventional configuration poses a limitation to its wide range application. Therefore, a renewed 7-level multilevel inverter topology is introduced incorporating the least number of unidirectional switches and gate trigger circuitry, thereby ensuring the minimum switching losses, reducing size and installation cost. The new topology is well suited for drives and renewable energy applications. The performance quality in terms of THD and switching losses of the new MLI is compared with conventional cascaded MLI and other existing 7-level reduced switch topologies using carrier-based PWM techniques. The results are validated using MATLAB/SIMULINK.

scholarly journals A Novel Symmetrical Multilevel Inverter with Reduced Switch Count

2020 ◽  
Vol 9 (4) ◽  
pp. 1651-1656
Keyword(s):  
Harmonic Distortion ◽  
Power Converter ◽  
Multilevel Inverter ◽  
Level Shift ◽  
Multilevel Inverters ◽  
Output Waveform ◽  
Switching Losses ◽  
Minimum Number ◽  
Converter Topologies ◽  
Inverter Topology

Multilevel inverters produced lot of interest in academia and industry as they are becoming feasible technology for number of applications. These are considered as the progressing power converter topologies. To generate a quality output waveform with minimum number of switches, reduced switch multilevel inverter topologies has come in focus. This paper introduces a modified symmetrical MLI with reduced component count thereby ensuring the minimum switching losses, reduced total harmonic distortion, Size and installation cost. By proper combination of switches it produces a staircase output waveform with low harmonic distortion. In this paper novel symmetrical inverter topology with reduced component count based on level shift phase opposition and disposition PWM (PODPWM) is proposed. The results are validated using MATLAB/SIMULINK.

Cascaded Multilevel Inverter IM Speed-Sensorless Vector Control System Based on MRAS Theory

2013 ◽  
Vol 344 ◽  
pp. 159-163
Author(s):  
Zhen Jun Lin ◽  
Sheng Hua Huang
Keyword(s):  
Vector Control ◽  
Induction Motor ◽  
Low Voltage ◽  
Multilevel Inverter ◽  
Speed Sensorless ◽  
Multilevel Inverters ◽  
Sensorless Vector Control ◽  
Simulation And Experiment ◽  
Vector Control System ◽  
Cascaded Multilevel Inverter

Cascaded multilevel inverters could realize high-voltage output based on a series connection of power cells which use standard low-voltage component configurations. This characteristic could achieve high-quality output voltage waveforms and input current waveforms. These merits are made for motor control, especially in the field of speed-sensorless vector control of induction motor based on the theory of MRAS. This paper constructs a simulation system with the help of MATLB/SIMULINK and a system combined cascaded H-bridge multilevel inverter with induction motor with the help of DSP and FPGA. The simulation and experiment results verified the superiority of cascaded multilevel inverter applied on the MRAS speed-sensorless vector control of induction motor.

scholarly journals MATLAB/simulink study of multi-level inverter topologies using minimized quantity of switches

2017 ◽  
Vol 7 (1.5) ◽  
pp. 209
Author(s):  
B.Vijaya Krishna ◽  
B. Venkata Prashanth ◽  
P. Sujatha
Keyword(s):  
Harmonic Distortion ◽  
Pulse Generation ◽  
Multilevel Inverter ◽  
Matlab Simulink ◽  
Multilevel Inverters ◽  
Energy Applications ◽  
Electrical Drives ◽  
Switching Losses ◽  
Trigger Circuit ◽  
Inverter Topology

Multilevel Inverters (MLI) have very good features when compared to Inverters. But using more switches in the conventional configuration will reduce its application in a wider range. For that reason a modified 7-level MLI Topology is presented. This new topology consists of less number of switches that can be reduced to the maximum extent and a separate gate trigger circuit. This will reduce the switching losses, reduce the size of the multilevel inverter, and cost of installation. This new topology can be used in Electrical drives and renewable energy applications. Performance of the new MLI is tested via. Total harmonic distortion. This construction structure of this multilevel inverter topology can also be increased for 9-level, 11-level and so on and simulated by the use of MATLAB/SIMULINK. A separate Carrier Based PWM Technique is used for the pulse generation in this configuration.

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