scholarly journals Investigation of a Superscalar Operand Stack Using FO4 and ASIC Wire-Delay Metrics

VLSI Design ◽  
2014 ◽  
Vol 2014 ◽  
pp. 1-13
Author(s):  
Christopher Bailey ◽  
Brendan Mullane
Keyword(s):  
Hot Spots ◽  
Reference Model ◽  
File Organization ◽  
Standard Cell Library ◽  
Cell Library ◽  
Future Improvement ◽  
Reported Study ◽  
Wide Issue ◽  
Wire Delay ◽  
Timing Simulation

Complexity in processor microarchitecture and the related issues of power density, hot spots and wire delay, are seen to be a major concern for design migration into low nanometer technologies of the future. This paper evaluates the hardware cost of an alternative to register-file organization, the superscalar stack issue array (SSIA). We believe this is the first such reported study using discrete stack elements. Several possible implementations are evaluated, using a 90 nm standard cell library as a reference model, yielding delay data and FO4 metrics. The evaluation, including reference to ASIC layout, RC extraction, and timing simulation, suggests a 4-wide issue rate of at least four Giga-ops/sec at 90 nm and opportunities for twofold future improvement by using more advanced design approaches.

Superconductor Standard Cell Library for Advanced EDA Design Flow

2021 ◽  
pp. 1-1
Author(s):  
Sukanya Sagarika Meher ◽  
Jushya Ravi ◽  
Mustafa Eren Celik ◽  
Stephen Miller ◽  
Anubhav Sahu ◽  
...  
Keyword(s):  
Design Flow ◽  
Standard Cell ◽  
Standard Cell Library ◽  
Cell Library

NMLib: A Nanomagnetic Logic Standard Cell Library

2021 ◽  
Author(s):  
Laysson Oliveira Luz ◽  
Jose Augusto M. Nacif ◽  
Ricardo S. Ferreira ◽  
Omar P. Vilela Neto
Keyword(s):  
Standard Cell ◽  
Standard Cell Library ◽  
Nanomagnetic Logic ◽  
Cell Library

scholarly journals Energy-Efficient Hardware Architectures for the Packet Data Convergence Protocol in LTE-Advanced Mobile Terminals

VLSI Design ◽  
2013 ◽  
Vol 2013 ◽  
pp. 1-15
Author(s):  
Shadi Traboulsi ◽  
Valerio Frascolla ◽  
Nils Pohl ◽  
Josef Hausner ◽  
Attila Bilgic
Keyword(s):  
Power Consumption ◽  
Energy Efficient ◽  
Reference Architecture ◽  
Least Significant Bit ◽  
Mobile Terminals ◽  
Standard Cell Library ◽  
Cell Library ◽  
Lte Advanced ◽  
Packet Data ◽  
Hardware Architectures

In this paper, we present and compare efficient low-power hardware architectures for accelerating the Packet Data Convergence Protocol (PDCP) in LTE and LTE-Advanced mobile terminals. Specifically, our work proposes the design of two cores: a crypto engine for the Evolved Packet System Encryption Algorithm (128-EEA2) that is based on the AES cipher and a coprocessor for the Least Significant Bit (LSB) encoding mechanism of the Robust Header Compression (ROHC) algorithm. With respect to the former, first we propose a reference architecture, which reflects a basic implementation of the algorithm, then we identify area and power bottle-necks in the design and finally we introduce and compare several architectures targeting the most power-consuming operations. With respect to the LSB coprocessor, we propose a novel implementation based on a one-hot encoding, thereby reducing hardware’s logic switching rate. Architectural hardware analysis is performed using Faraday’s 90 nm standard-cell library. The obtained results, when compared against the reference architecture, show that these novel architectures achieve significant improvements, namely, 25% in area and 35% in power consumption for the 128-EEA2 crypto-core, and even more important reductions are seen for the LSB coprocessor, that is, 36% in area and 50% in power consumption.

Approximate Full Adders for Energy Efficient Image Processing Applications

2021 ◽  
pp. 2150235
Author(s):  
M. C. Parameshwara
Keyword(s):  
Energy Efficient ◽  
State Of The Art ◽  
Signal To Noise Ratio ◽  
Full Adder ◽  
Signal To Noise ◽  
Design Metrics ◽  
Standard Cell Library ◽  
Cell Library ◽  
Fair Comparison ◽  
Power Delay Product

This paper proposes six novel approximate 1-bit full adders (AFAs) for inexact computing. The six novel AFAs namely AFA1, AFA2, AFA3, AFA4, AFA5, and AFA6 are derived from state-of-the-art exact 1-bit full adder (EFA) architectures. The performance of these AFAs is compared with reported AFAs (RAAs) in terms of design metrics (DMs) and peak-signal-to-noise-ratio (PSNR). The DMs under consideration are power, delay, power-delay-product (PDP), energy-delay-product (EDP), and area. For a fair comparison, the EFAs and proposed AFAs along with RAAs are described in Verilog, simulated, and synthesized using Cadences’ RC tool, using generic 180 nm standard cell library. The unconstrained synthesis results show that: among all the proposed AFAs, the AFA1 and AFA2 are found to be energy-efficient adders with high PSNR. The AFA1 has a total [Formula: see text][Formula: see text][Formula: see text]W, [Formula: see text][Formula: see text]ps, [Formula: see text][Formula: see text]fJ, [Formula: see text][Formula: see text]Js, [Formula: see text][Formula: see text][Formula: see text]m2, and [Formula: see text][Formula: see text]dB. And the AFA2 has the total [Formula: see text][Formula: see text][Formula: see text]W, [Formula: see text][Formula: see text]ps, [Formula: see text][Formula: see text]fJ, [Formula: see text][Formula: see text]Js, [Formula: see text][Formula: see text][Formula: see text]m2, and [Formula: see text][Formula: see text]dB.

Sign in / Sign up

Export Citation Format

Share Document