scholarly journals High Level Synthesis FPGA Implementation of the Jacobi Algorithm to Solve the Eigen Problem

2015 ◽  
Vol 2015 ◽  
pp. 1-11 ◽  
Author(s):  
Ignacio Bravo ◽  
César Vázquez ◽  
Alfredo Gardel ◽  
José L. Lázaro ◽  
Esther Palomar
Keyword(s):  
High Level Synthesis ◽  
Eigenvalue Decomposition ◽  
Real Time Processing ◽  
Low Level ◽  
Hardware Implementations ◽  
Jacobi Algorithm ◽  
Field Programmable ◽  
Hardware Architectures ◽  
High Level ◽  
Hardware Designs

We present a hardware implementation of the Jacobi algorithm to compute the eigenvalue decomposition (EVD). The computation of eigenvalues and eigenvectors has many applications where real time processing is required, and thus hardware implementations are often mandatory. Some of these implementations have been carried out with field programmable gate array (FPGA) devices using low level register transfer level (RTL) languages. In the present study, we used the Xilinx Vivado HLS tool to develop a high level synthesis (HLS) design and evaluated different hardware architectures. After analyzing the design for different input matrix sizes and various hardware configurations, we compared it with the results of other studies reported in the literature, concluding that although resource usage may be higher when HLS tools are used, the design performance is equal to or better than low level hardware designs.

scholarly journals Optimization of Advanced Encryption Standard (AES) Using Vivado High Level Synthesis (HLS)

10.29007/x3tx ◽  
2019 ◽  
Author(s):  
Luka Daoud ◽  
Fady Hussein ◽  
Nader Rafla
Keyword(s):  
High Level Synthesis ◽  
Advanced Encryption Standard ◽  
Data Confidentiality ◽  
Maximum Throughput ◽  
Loop Unrolling ◽  
Aes Algorithm ◽  
Hardware Implementations ◽  
High Level ◽  
Dedicated Hardware ◽  
Vivado Hls

Advanced Encryption Standard (AES) represents a fundamental building module of many network security protocols to ensure data confidentiality in various applications ranging from data servers to low-power hardware embedded systems. In order to optimize such hardware implementations, High-Level Synthesis (HLS) provides flexibility in designing and rapid optimization of dedicated hardware to meet the design constraints. In this paper, we present the implementation of AES encryption processor on FPGA using Xilinx Vivado HLS. The AES architecture was analyzed and designed by loop unrolling, and inner-round and outer-round pipelining techniques to achieve a maximum throughput of the AES algorithm up to 1290 Mbps (Mega bit per second) with very significant low resources of 3.24% slices of the FPGA, achieving 3 Mbps per slice area.

A High-Throughput Architecture for the SHA-256/224 Compliant With the DSRC Standard

2019 ◽  
Vol 10 (1) ◽  
pp. 98-118
Author(s):  
Imed Saad Ben Dhaou ◽  
Hannu Tenhunen
Keyword(s):  
High Throughput ◽  
Short Range ◽  
State Of The Art ◽  
High Level Synthesis ◽  
Data Flow Graph ◽  
Transformation Techniques ◽  
Safety Message ◽  
Dedicated Short Range Communication ◽  
Field Programmable ◽  
High Level

This article presents a word serial retimed architecture for the SHA-256/224 algorithm. The architecture is compliant with the dedicated-short range communication for safety message authentications. We elaborate three-operand adder architectures suitable for field programmable gate array implementation. Several transformation techniques at the data-flow-graph level have been used to derive the architecture. Synthesis results show that the architecture has high throughput/ slice value compared with state-of-the-art SHA-256 implementations. The article also promulgates a comparison between high-level synthesis and RTL design.

scholarly journals Implementation of integrated design space exploration of scheduling, allocation and binding in high level synthesis using multi structure genetic algorithm

2021 ◽  
Author(s):  
Michael Gebremariam
Keyword(s):  
Genetic Algorithm ◽  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration ◽  
Integrated Design ◽  
High Level Synthesis ◽  
C Language ◽  
Low Level ◽  
Wide Range ◽  
High Level

The objective of this project is to develop a software tool which assists in comparison of a work known as "M-GenESys: Multi Structure Genetic Algorithm based Design Space Exploration System for Integrated Scheduling, Allocation and Binding in High Level Synthesis" with another well established GA approach known as "A Generic Algorithm for the Design Space Exploration of Data paths During High-Level Synthesis". Two sets of software are developed based on both approaches using Microsoft Visual 2005 C# language. The C# language is an object-oriented language that is aimed at enabling programmers to quickly develop a wide range of applications on the Microsoft .NET platform. The goal of C# and the .NET platform is to shorten development time by freeing the developer from worrying about several low level plumbing issues such as memory equipment, type safety issues, building low level libraries, array bound checking, etc., thus allowing developers to actually spend their time and energy working on the application and business logic.

scholarly journals High-Level Synthesis of Multiclass SVM Using Code Refactoring to Classify Brain Cancer from Hyperspectral Images

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1494 ◽  
Author(s):  
Abelardo Baez ◽  
Himar Fabelo ◽  
Samuel Ortega ◽  
Giordana Florimbi ◽  
Emanuele Torti ◽  
...  
Keyword(s):  
Brain Cancer ◽  
Research Field ◽  
Hyperspectral Images ◽  
High Level Synthesis ◽  
Support Vector ◽  
Svm Classifier ◽  
Code Refactoring ◽  
Field Programmable ◽  
And Performance ◽  
High Level

Currently, high-level synthesis (HLS) methods and tools are a highly relevant area in the strategy of several leading companies in the field of system-on-chips (SoCs) and field programmable gate arrays (FPGAs). HLS facilitates the work of system developers, who benefit from integrated and automated design workflows, considerably reducing the design time. Although many advances have been made in this research field, there are still some uncertainties about the quality and performance of the designs generated with the use of HLS methodologies. In this paper, we propose an optimization of the HLS methodology by code refactoring using Xilinx SDSoCTM (Software-Defined System-On-Chip). Several options were analyzed for each alternative through code refactoring of a multiclass support vector machine (SVM) classifier written in C, using two different Zynq®-7000 SoC devices from Xilinx, the ZC7020 (ZedBoard) and the ZC7045 (ZC706). The classifier was evaluated using a brain cancer database of hyperspectral images. The proposed methodology not only reduces the required resources using less than 20% of the FPGA, but also reduces the power consumption −23% compared to the full implementation. The speedup obtained of 2.86× (ZC7045) is the highest found in the literature for SVM hardware implementations.

AN EVOLUTIONARY ALGORITHM FOR THE ALLOCATION PROBLEM IN HIGH-LEVEL SYNTHESIS

2005 ◽  
Vol 14 (02) ◽  
pp. 347-366 ◽  
Author(s):  
HAIDAR M. HARMANANI ◽  
RONY SALIBA
Keyword(s):  
Evolutionary Algorithm ◽  
Allocation Problem ◽  
High Level Synthesis ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Functional Units ◽  
High Level ◽  
The Cost ◽  
Short Time

This paper presents an evolutionary algorithm to solve the datapath allocation problem in high-level synthesis. The method performs allocation of functional units, registers, and multiplexers in addition to controller synthesis with the objective of minimizing the cost of hardware resources. The system handles multicycle functional units as well as structural pipelining. The proposed method was implemented using C++ on a Linux workstation. We tested our method on a set of high-level synthesis benchmarks, all yielding good solutions in a short time. An integration path to Field Programmable Gate Arrays (FPGAs) is provided through VHDL.

scholarly journals GPU implementation of restricted Boltzmann machines with application to view classification in sports videos

2021 ◽  
Author(s):  
Andreas Fred Bernitzke
Keyword(s):  
Genetic Algorithm ◽  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration ◽  
High Level Synthesis ◽  
Restricted Boltzmann Machines ◽  
C Language ◽  
Low Level ◽  
Wide Range ◽  
High Level

The objective of this project is to develop a software tool which assists in comparison of a work known as "M-GenESys: Multi Structure Genetic Algorithm based Design Space Exploration System for Integrated Scheduling, Allocation and Binding in High Level Synthesis" with another well established GA approach known as "A Genetic Algorithm for the Design Space Exploration of Data paths During High-Level Synthesis". Two sets of Software are developed based on both approaches using Microsoft visual 2005,C# language. The C# language is an object-oriented language that is aimed at enabling programmers to quickly develop a wide range of applications on the Microsoft .NET platform. The goal of C# and the .NET platform is to shorten development time by freeing the developer from worrying about several low level plumbing issues such as memory management, type safety issues, building low level libraries, array bounds checking, etc. thus allowing developers to actually spend their time and energy working on the application and business logic.

scholarly journals Implementation of an LDPC decoder for IEEE 802.11n using VivadoTM High-Level Synthesis

2021 ◽  
Vol 8 ◽  
pp. 1-4
Author(s):  
Ernest Scheiber ◽  
Guido H. Bruck ◽  
Peter Jung
Keyword(s):  
Forward Error Correction ◽  
Implementation Process ◽  
Research Topic ◽  
High Level Synthesis ◽  
Ldpc Decoder ◽  
The Past ◽  
High Level ◽  
Forward Error ◽  
Hardware Designs ◽  
High Processing

The increasing complexity of hardware designs calls for design methodolgies that use more abstract design entries and increased automation of the implementation process. Highlevel synthesis (HLS) has been a research topic for the past 20 years, and current tools, such as Xilinx VivadoTM HLS promise to bring HLS to widespread use. In this paper we use Xilinx VivadoTMHLS to design an LDPC decoder for 802.11n. Forward error correction decoders are typically implemented in hardware due to the high processing requirements and therefore an LDPC decoder is an appropriate example to demonstrate the power of high-level synthesis

scholarly journals Implementation of integrated design space exploration of scheduling, allocation and binding in high level synthesis using multi structure genetic algorithm

2021 ◽  
Author(s):  
Michael Gebremariam
Keyword(s):  
Genetic Algorithm ◽  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration ◽  
Integrated Design ◽  
High Level Synthesis ◽  
C Language ◽  
Low Level ◽  
Wide Range ◽  
High Level

The objective of this project is to develop a software tool which assists in comparison of a work known as "M-GenESys: Multi Structure Genetic Algorithm based Design Space Exploration System for Integrated Scheduling, Allocation and Binding in High Level Synthesis" with another well established GA approach known as "A Generic Algorithm for the Design Space Exploration of Data paths During High-Level Synthesis". Two sets of software are developed based on both approaches using Microsoft Visual 2005 C# language. The C# language is an object-oriented language that is aimed at enabling programmers to quickly develop a wide range of applications on the Microsoft .NET platform. The goal of C# and the .NET platform is to shorten development time by freeing the developer from worrying about several low level plumbing issues such as memory equipment, type safety issues, building low level libraries, array bound checking, etc., thus allowing developers to actually spend their time and energy working on the application and business logic.

scholarly journals High-Level Synthesis: Productivity, Performance, and Software Constraints

2012 ◽  
Vol 2012 ◽  
pp. 1-14 ◽  
Author(s):  
Yun Liang ◽  
Kyle Rupnow ◽  
Yinan Li ◽  
Dongbo Min ◽  
Minh N. Do ◽  
...  
Keyword(s):  
Stereo Matching ◽  
Feature Matching ◽  
General Purpose ◽  
High Level Synthesis ◽  
Future Directions ◽  
Hardware Implementations ◽  
Rtl Design ◽  
Order Of Magnitude ◽  
High Level

FPGAs are an attractive platform for applications with high computation demand and low energy consumption requirements. However, design effort for FPGA implementations remains high—often an order of magnitude larger than design effort using high-level languages. Instead of this time-consuming process, high-level synthesis (HLS) tools generate hardware implementations from algorithm descriptions in languages such as C/C++ and SystemC. Such tools reduce design effort: high-level descriptions are more compact and less error prone. HLS tools promise hardware development abstracted from software designer knowledge of the implementation platform. In this paper, we present an unbiased study of the performance, usability and productivity of HLS using AutoPilot (a state-of-the-art HLS tool). In particular, we first evaluate AutoPilot using the popular embedded benchmark kernels. Then, to evaluate the suitability of HLS on real-world applications, we perform a case study of stereo matching, an active area of computer vision research that uses techniques also common for image denoising, image retrieval, feature matching, and face recognition. Based on our study, we provide insights on current limitations of mapping general-purpose software to hardware using HLS and some future directions for HLS tool development. We also offer several guidelines for hardware-friendly software design. For popular embedded benchmark kernels, the designs produced by HLS achieve 4X to 126X speedup over the software version. The stereo matching algorithms achieve between 3.5X and 67.9X speedup over software (but still less than manual RTL design) with a fivefold reduction in design effort versus manual RTL design.

Sign in / Sign up

Export Citation Format

Share Document