An Efficient Image Enlargement Method for Image Sensors of Mobile in Embedded Systems

Main challenges for image enlargement methods in embedded systems come from the requirements of good performance, low computational cost, and low memory usage. This paper proposes an efficient image enlargement method which can meet these requirements in embedded system. Firstly, to improve the performance of enlargement methods, this method extracts different kind of features for different morphologies with different approaches. Then, various dictionaries based on different kind of features are learned, which represent the image in a more efficient manner. Secondly, to accelerate the enlargement speed and reduce the memory usage, this method divides the atoms of each dictionary into several clusters. For each cluster, separate projection matrix is calculated. This method reformulates the problem as a least squares regression. The high-resolution (HR) images can be reconstructed based on a few projection matrixes. Numerous experiment results show that this method has advantages such as being efficient and real-time and having less memory cost. These advantages make this method easy to implement in mobile embedded system.

Download Full-text

Control-Scheduling Codesign for NCS based Fuzzy Systems

International Journal of Computers Communications & Control ◽

10.15837/ijccc.2018.2.3243 ◽

2018 ◽

Vol 13 (2) ◽

pp. 251-267 ◽

Cited By ~ 2

Author(s):

Paul Erick Mendez-Monroy ◽

Israel Sanchez Dominguez ◽

Ali Bassam ◽

Oscar May Tzuc

Keyword(s):

Embedded System ◽

Fuzzy Controller ◽

Hybrid Control ◽

Computational Cost ◽

Sampling Period ◽

Networked Control System ◽

Fuzzy Scheduling ◽

The Stability ◽

Scheduler Design ◽

Low Computational Cost

In the present paper, a fuzzy codesign approach is proposed to deal with the controller and scheduler design for a networked control system which is physically distributed with a shared communication network. The proposed fuzzy controller is applied to generate the control with different sampling-actuation periods, the configuration supposes a strict actuation period disappears the jitter. The proposed fuzzy scheduling is designed to select the sampling-actuation period. So, the fuzzy codesign reduces the rate of transmission when the system is stable through the scheduler while the controller adjusts the control signal. The fuzzy codesign guarantees the stability of all the system if the network uncertainties do not exceed an upper bound and is a low computational cost method implemented with an embedded system. An unstable, nonlinear system is used to evaluate the proposed approach and compared to a hybrid control, the results show greater robustness to multiple lost packets and time delays much larger than the sampling period. (This paper is an extension of [20]. Reprinted (partial) and extended, with permission based on License Number 4275590998661 IEEE, from "Electrical Engineering, Computing Science and Automatic Control, 2017 14th International Conference on")

Download Full-text

A Mix-resolution Bone-related Statistical Deformable Model (mBr-SDM) for Soft Tissue Prediction in Orthognathic Surgery Planning

10.54294/vg46tm ◽

2008 ◽

Author(s):

He Qizhen ◽

Ip Horace ◽

James Xia

Keyword(s):

Finite Element ◽

High Resolution ◽

Orthognathic Surgery ◽

Computational Cost ◽

Element Model ◽

Regions Of Interest ◽

Deformable Model ◽

Deformation Region ◽

Low Computational Cost ◽

Main Deformation

In this paper, we propose a Mix-resolution Bone-related Statistical Deformable Model (mBr-SDM) to improve the predicting accuracy of orthognathic surgery, particularly for the main deformation region. Mix-resolution Br-SDM consists of two separate Br-SDM of different resolutions: a high-resolution Br-SDM which is trained with more samples to capture the detail deforming variations in the main deforming regions of interest, together with a low-resolution Br-SDM which is trained with a smaller number of samples to capture the major variations of the remaining facial points. The experiments have shown that the mix-resolution Br-SDM is able to significantly reduce the predicting error compared with the corresponding Finite Element Model, while giving a low computational cost which is characteristic of the SDM approach.

Download Full-text

A Two-Layer Component-Based Allocation for Embedded Systems with GPUs

Designs ◽

10.3390/designs3010006 ◽

2019 ◽

Vol 3 (1) ◽

pp. 6

Author(s):

Gabriel Campeanu ◽

Mehrdad Saadatmand

Keyword(s):

Embedded Systems ◽

Embedded System ◽

Heterogeneous Systems ◽

Connected Components ◽

Memory Usage ◽

Allocation Mechanism ◽

Component Based Development ◽

Allocation Process ◽

Gpu Architectures ◽

High Level

Component-based development is a software engineering paradigm that can facilitate the construction of embedded systems and tackle its complexities. The modern embedded systems have more and more demanding requirements. One way to cope with such a versatile and growing set of requirements is to employ heterogeneous processing power, i.e., CPU–GPU architectures. The new CPU–GPU embedded boards deliver an increased performance but also introduce additional complexity and challenges. In this work, we address the component-to-hardware allocation for CPU–GPU embedded systems. The allocation for such systems is much complex due to the increased amount of GPU-related information. For example, while in traditional embedded systems the allocation mechanism may consider only the CPU memory usage of components to find an appropriate allocation scheme, in heterogeneous systems, the GPU memory usage needs also to be taken into account in the allocation process. This paper aims at decreasing the component-to-hardware allocation complexity by introducing a two-layer component-based architecture for heterogeneous embedded systems. The detailed CPU–GPU information of the system is abstracted at a high-layer by compacting connected components into single units that behave as regular components. The allocator, based on the compacted information received from the high-level layer, computes, with a decreased complexity, feasible allocation schemes. In the last part of the paper, the two-layer allocation method is evaluated using an existing embedded system demonstrator; namely, an underwater robot.

Download Full-text

Complex-Valued Reservoir Computing for Interferometric SAR Applications with Low Computational Cost and High Resolution

IEEE Journal of Selected Topics in Applied Earth Observations and Remote Sensing ◽

10.1109/jstars.2021.3102620 ◽

2021 ◽

pp. 1-1

Author(s):

Bungo Konishi ◽

Akira Hirose ◽

Ryo Natsuaki

Keyword(s):

High Resolution ◽

Computational Cost ◽

Reservoir Computing ◽

Interferometric Sar ◽

Complex Valued ◽

Low Computational Cost

Download Full-text

Software System Development to Diagnose Heart Diseases

10.5753/latinoware.2019.10353 ◽

2019 ◽

Author(s):

Renan Yuji Koga Ferreira ◽

Guilherme Camargo Fabricio De Melloy ◽

Fabio Sakurayz ◽

Wesley Attrot

Keyword(s):

Feature Extraction ◽

Early Detection ◽

Embedded System ◽

Wavelet Transforms ◽

System Development ◽

Heart Diseases ◽

Low Cost ◽

Computational Cost ◽

Extraction Algorithm ◽

Low Computational Cost

Many deaths are caused from heart diseases and several of them could be prevented with early detection. Many people do not have conditions to seek for a doctor or sometimes there are not enough physicians to attend them. In order to detect heart diseases we are developing an electrocardiogram feature extraction algorithm using wavelet transforms prioritizing a low computational cost. This algorithm will be integrated in an embedded system that is under development. This system is going to be accessible, portable and have low cost, because we intend to assist people, mostly those who live in precarious regions, that do not have a physician to attend them. To execute tests on our algorithm we will use the ECG records from MITBIH database and after that we will classify the heartbeats in order to detect anomalies on them.

Download Full-text

Compiler-Aided Run-Time Performance Speed-Up in Super-Scalar Processor

10.28945/3391 ◽

2009 ◽

Author(s):

Moshe Pelleh

Keyword(s):

Embedded Systems ◽

Embedded System ◽

General Purpose ◽

Experimental Results ◽

Medium Size ◽

Organic System ◽

Software Application ◽

Organic Systems ◽

Special Cases ◽

Run Time

In our world, where most systems become embedded systems, the approach of designing embedded systems is still frequently similar to the approach of designing organic systems (or not embedded systems). An organic system, like a personal computer or a work station, must be able to run any task submitted to it at any time (with certain constrains depending on the machine). Consequently, it must have a sophisticated general purpose Operating System (OS) to schedule, dispatch, maintain and monitor the tasks and assist them in special cases (particularly communication and synchronization between them and with external devices). These OSs require an overhead on the memory, on the cache and on the run time. Moreover, generally they are task oriented rather than machine oriented; therefore the processor's throughput is penalized. On the other hand, an embedded system, like an Anti-lock Braking System (ABS), executes always the same software application. Frequently it is a small or medium size system, or made up of several such systems. Many small or medium size embedded systems, with limited number of tasks, can be scheduled by our proposed hardware architecture, based on the Motorola 500MHz MPC7410 processor, enhancing its throughput and avoiding the software OS overhead, complexity, maintenance and price. Encouraged by our experimental results, we shall develop a compiler to assist our method. In the meantime we will present here our proposal and the experimental results.

Download Full-text

A Novel Rail-Network Hardware Simulator for Embedded System Programming

Electronics ◽

10.3390/electronics10010013 ◽

2020 ◽

Vol 10 (1) ◽

pp. 13

Author(s):

Balaji M ◽

Chandrasekaran M ◽

Vaithiyanathan Dhandapani

Keyword(s):

Embedded Systems ◽

Embedded System ◽

Real Time ◽

Learning Outcomes ◽

Real World ◽

Time Constraints ◽

Network Simulator ◽

Practical Applications ◽

Rail Network ◽

Knowledge Enhancement

A Novel Rail-Network Hardware with simulation facilities is presented in this paper. The hardware is designed to facilitate the learning of application-oriented, logical, real-time programming in an embedded system environment. The platform enables the creation of multiple unique programming scenarios with variability in complexity without any hardware changes. Prior experimental hardware comes with static programming facilities that focus the students’ learning on hardware features and programming basics, leaving them ill-equipped to take up practical applications with more real-time constraints. This hardware complements and completes their learning to help them program real-world embedded systems. The hardware uses LEDs to simulate the movement of trains in a network. The network has train stations, intersections and parking slots where the train movements can be controlled by using a 16-bit Renesas RL78/G13 microcontroller. Additionally, simulating facilities are provided to enable the students to navigate the trains by manual controls using switches and indicators. This helps them get an easy understanding of train navigation functions before taking up programming. The students start with simple tasks and gradually progress to more complicated ones with real-time constraints, on their own. During training, students’ learning outcomes are evaluated by obtaining their feedback and conducting a test at the end to measure their knowledge acquisition during the training. Students’ Knowledge Enhancement Index is originated to measure the knowledge acquired by the students. It is observed that 87% of students have successfully enhanced their knowledge undergoing training with this rail-network simulator.

Download Full-text

A Generalization Performance Study Using Deep Learning Networks in Embedded Systems

Sensors ◽

10.3390/s21041031 ◽

2021 ◽

Vol 21 (4) ◽

pp. 1031

Author(s):

Joseba Gorospe ◽

Rubén Mulero ◽

Olatz Arbelaitz ◽

Javier Muguerza ◽

Miguel Ángel Antón

Keyword(s):

Deep Learning ◽

Embedded Systems ◽

Embedded System ◽

General Purpose ◽

Learning Networks ◽

Performance Study ◽

Learning Techniques ◽

Wide Range ◽

Learning Architectures

Deep learning techniques are being increasingly used in the scientific community as a consequence of the high computational capacity of current systems and the increase in the amount of data available as a result of the digitalisation of society in general and the industrial world in particular. In addition, the immersion of the field of edge computing, which focuses on integrating artificial intelligence as close as possible to the client, makes it possible to implement systems that act in real time without the need to transfer all of the data to centralised servers. The combination of these two concepts can lead to systems with the capacity to make correct decisions and act based on them immediately and in situ. Despite this, the low capacity of embedded systems greatly hinders this integration, so the possibility of being able to integrate them into a wide range of micro-controllers can be a great advantage. This paper contributes with the generation of an environment based on Mbed OS and TensorFlow Lite to be embedded in any general purpose embedded system, allowing the introduction of deep learning architectures. The experiments herein prove that the proposed system is competitive if compared to other commercial systems.

Download Full-text

Singular Value Decomposition in Embedded Systems Based on ARM Cortex-M Architecture

Electronics ◽

10.3390/electronics10010034 ◽

2020 ◽

Vol 10 (1) ◽

pp. 34

Author(s):

Michele Alessandrini ◽

Giorgio Biagetti ◽

Paolo Crippa ◽

Laura Falaschetti ◽

Lorenzo Manoni ◽

...

Keyword(s):

Embedded Systems ◽

Singular Value Decomposition ◽

Embedded System ◽

Mimo Systems ◽

Singular Value ◽

Measurement Unit ◽

Comprehensive Treatment ◽

Mathematical Tool ◽

Value Decomposition ◽

Speed Accuracy

Singular value decomposition (SVD) is a central mathematical tool for several emerging applications in embedded systems, such as multiple-input multiple-output (MIMO) systems, data analytics, sparse representation of signals. Since SVD algorithms reduce to solve an eigenvalue problem, that is computationally expensive, both specific hardware solutions and parallel implementations have been proposed to overcome this bottleneck. However, as those solutions require additional hardware resources that are not in general available in embedded systems, optimized algorithms are demanded in this context. The aim of this paper is to present an efficient implementation of the SVD algorithm on ARM Cortex-M. To this end, we proceed to (i) present a comprehensive treatment of the most common algorithms for SVD, providing a fairly complete and deep overview of these algorithms, with a common notation, (ii) implement them on an ARM Cortex-M4F microcontroller, in order to develop a library suitable for embedded systems without an operating system, (iii) find, through a comparative study of the proposed SVD algorithms, the best implementation suitable for a low-resource bare-metal embedded system, (iv) show a practical application to Kalman filtering of an inertial measurement unit (IMU), as an example of how SVD can improve the accuracy of existing algorithms and of its usefulness on a such low-resources system. All these contributions can be used as guidelines for embedded system designers. Regarding the second point, the chosen algorithms have been implemented on ARM Cortex-M4F microcontrollers with very limited hardware resources with respect to more advanced CPUs. Several experiments have been conducted to select which algorithms guarantee the best performance in terms of speed, accuracy and energy consumption.

Download Full-text