scholarly journals Design and analysis of dedicated real-time clock for customized microcontroller unit

2019 ◽  
Vol 14 (2) ◽  
pp. 796
Author(s):  
M.N. A.M. Alias ◽  
S. N. Mohyar ◽  
M. N. Isa ◽  
A. Harun ◽  
A. B. Jambek ◽  
...  
Keyword(s):  
Real Time ◽  
Frequency Divider ◽  
Hardware Description Language ◽  
Description Language ◽  
Real Time Clock ◽  
Hardware Description ◽  
On Chip ◽  
Microcontroller Unit ◽  
Bus Architecture ◽  
Precise Time

<span>In this paper, a Real Time Clock (RTC) system for a dedicated microcontroller is proposed to provide the customized microcontroller its own time and date system. The RTC is developed using Verilog Hardware Description Language (HDL) and simulated using Synopsys software. This RTC is developed with standard Advance Peripheral Bus (APB) to be interfacing with the microcontroller through Advanced Microcontroller Bus Architecture (AMBA). This RTC will be used as an on-chip RTC in the microcontroller system to provide precise time and date which can be used for various applications. The basic architecture of RTC, APB standard for interfacing the RTC with AMBA bus, and the result in term of RTL, waveform, and layout will be discussed in this documentation. For this research, the part covered is on the logic part of the RTC that is bus interface, register, frequency divider and counter.</span>

scholarly journals Design of AMBA AXI4 protocol for System-on-Chip communication

2012 ◽  
pp. 38-42
Author(s):  
Shaila S Math ◽  
Manjula R B
Keyword(s):  
System On Chip ◽  
Hardware Description Language ◽  
Test Cases ◽  
Description Language ◽  
Write Response ◽  
Hardware Description ◽  
Simulation Results ◽  
On Chip ◽  
Ip Blocks ◽  
Bus Architecture

Advanced microcontroller bus architecture (AMBA) protocol family provides metric-driven verification of protocol compliance, enabling comprehensive testing of interface intellectual property (IP) blocks and system-on-chip (SoC) designs. The AMBA advanced extensible interface 4 (AXI4) update to AMBA AXI3 includes the following: support for burst lengths up to 256 beats, updated write response requirements, removal of locked transactions and AXI4 also includes information on the interoperability of components. AMBA AXI4 protocol system supports 16 masters and 16 slaves interfacing. This paper presents a work aimed to design the AMBA AXI4 protocol modeled in Verilog hardware description language (HDL) and simulation results for read and write operation of data and address are shown in Verilog compiler simulator (VCS) tool. The operating frequency is set to 100MHz. Two test cases are run to perform multiple read and multiple write operations. To perform single read operation module takes 160ns and for single write operation it takes 565ns.

scholarly journals A Real Time Algorithm for Versatile Mode Parking System and Its Implementation on FPGA Board

2022 ◽  
Vol 12 (2) ◽  
pp. 655
Author(s):  
Baligh Naji ◽  
Chokri Abdelmoula ◽  
Mohamed Masmoudi
Keyword(s):  
Real Time ◽  
Evaluation Process ◽  
Time Algorithm ◽  
Hardware Description Language ◽  
Optimal Solutions ◽  
Description Language ◽  
Parking System ◽  
Parking Lot ◽  
Field Programmable ◽  
Hardware Description

This paper presents the design and development of a technique for an Autonomous and Versatile mode Parking System (AVPS) that combines a various number of parking modes. The proposed approach is different from that of many developed parking systems. Previous research has focused on choosing only a parking lot starting from two parking modes (which are parallel and perpendicular). This research aims at developing a parking system that automatically chooses a parking lot starting from four parking modes. The automatic AVPS was proposed for the car-parking control problem, and could be potentially exploited for future vehicle generation. A specific mode can be easily computed using the proposed strategy. A variety of candidate modes could be generated using one developed real time VHDL (VHSIC Hardware Description Language) algorithm providing optimal solutions with performance measures. Based on simulation and experimental results, the AVPS is able to find and recognize in advance which parking mode to select. This combination describes full implementation on a mobile robot, such as a car, based on a specific FPGA (Field-Programmable Gate Array) card. To prove the effectiveness of the proposed innovation, an evaluation process comparing the proposed technique with existing techniques was conducted and outlined.

scholarly journals New Structure of Test Pattern Generator Stimulating Crosstalks in Bus-type Connections

2015 ◽  
Vol 61 (1) ◽  
pp. 67-75
Author(s):  
Tomasz Garbolino
Keyword(s):  
Test Pattern ◽  
Pattern Generator ◽  
System On Chip ◽  
Hardware Description Language ◽  
Test Sequence ◽  
Description Language ◽  
Hardware Description ◽  
Parameterized Model ◽  
On Chip ◽  
Operation Frequency

Abstract The paper discloses the idea of a new structure for a Test Pattern Generator (TPG) for detection of crosstalk faults that may happen to bus-type interconnections between built-in blocks within a System-on-Chip structure. The new idea is an improvement of the TPG design proposed by the author in one of the previous studies. The TPG circuit is meant to generate test sequences that guarantee detection of all crosstalk faults with the capacitive nature that may occur between individual lines within an interconnecting bus. The study comprises a synthesizable and parameterized model developed for the presented TPG in the VLSI Hardware Description Language (VHDL) with further investigation of properties and features of the offered module. The significant advantages of the proposed TPG structure include less area occupied on a chip and higher operation frequency as compared to other solutions. In addition, the design demonstrates good scalability in terms of both the hardware overhead and the length of the generated test sequence

Efficient Conversion Technique from Redundant Binary to NonRedundant Binary Representation

2017 ◽  
Vol 26 (09) ◽  
pp. 1750135 ◽  
Author(s):  
Ranjan Kumar Barik ◽  
Manoranjan Pradhan ◽  
Rutuparna Panda
Keyword(s):  
Final Stage ◽  
Hardware Description Language ◽  
Binary Representation ◽  
Description Language ◽  
Power Product ◽  
Efficient Conversion ◽  
Look Ahead ◽  
Hardware Description ◽  
Sign Extension ◽  
Cadence Tool

Redundant Binary (RB) to Two’s Complement (TC) converter offers nonredundant representation. However, the sign bit of TC representation has to be handled using nonstandard hardware blocks. The concept of Inverted encoding of negative weighted bits (IEN) eliminates the need of sign extension and offers design only using predefined hardware blocks. NonRedundant Binary (NRB) representation refers to both conventional and IEN representations. The NRB representation is also useful considering problem related to shifting in Carry Save (CS) representation of a RB number. In this paper, we have proposed two new conversion circuits for RB to NRB representation. The proposed circuits of the RB to NRB converter are coded in Verilog Hardware Description language (HDL) and synthesized using the Encounter(R) RTL Compiler RC13.10 v13.10-s006_1 of Cadence tool considering ASIC platform. Considering 64 bits’ operand, the delay power product performances of proposed one-bit and two-bit computations offer improvement of almost 29.9% and 47%, respectively as compared to Carry-Look-Ahead (CLA). The proposed one-bit converter is also applied in the final stage of the Modified Redundant Binary Adder (MRBA). The 32-bit MRBA offers a delay improvement of 7.87% replacing conventional converter with proposed one-bit converter in same FPGA 4vfx12sf363-12 device.

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