scholarly journals Efficient TCAM design based on dual port SRAM on FPGA

2021 ◽  
Vol 22 (1) ◽  
pp. 104
Author(s):  
Triet Nguyen ◽  
Kiet Ngo ◽  
Nguyen Trinh ◽  
Bao Bui ◽  
Linh Tran ◽  
...  
Keyword(s):  
Associative Memory ◽  
High Speed ◽  
Memory Storage ◽  
Content Addressable Memory ◽  
Ternary Content Addressable Memory ◽  
Trade Offs ◽  
Search Data

<span><span>Ternary content addressable memory (TCAM) is a memory that allows high speed searching for data. Not only it is acknowledged as associative memory/storage but also TCAM can compare input searching content (key) against a collection of accumulated data and return the matching address which compatible with this input search data. SRAM-based TCAM utilizes and allocates blocks RAM to perform application of TCAM on FPGA hardware. This paper presents a design of 480×104 bit SRAM-based TCAM on altera cyclone IV FPGA. Our design achieved lookup rate over 150 millions input search data and update speed at 75 million rules per second. The architecture is configurable, allowing various performance trade-offs to be exploited for different ruleset characteristics</span>.</span>

scholarly journals Low Power Implementation Of Ternary Content Addressable Memory (TCAM)

2019 ◽  
Vol 9 (1S3) ◽  
pp. 455-460
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Clock Cycle ◽  
Reversible Logic ◽  
Ultra Low Power ◽  
Content Addressable Memory ◽  
Power Characteristics ◽  
Ternary Content Addressable Memory ◽  
Network Routers

In network routers, Ternary Content Addressable Memory (TCAM)[1] based search engines take an important role. One of the improved versions of Content Addressable Memory (CAM) is TCAM. For high speed and broader searching operation TCAM is used. Unlike normal CAM, TCAM has 3 logic states: 0, 1, ‘X’. In TCAM within one single clock cycle, search operation can be performed. That is why it is called special type of memory. Also, quick search ability is one of the popular features of TCAM. To compare the search and stored data, TCAM array acts parallel in every location. But high power dissipation is the main disadvantage of TCAM. To overcome this power dissipation in this paper we proposed a low power TCAM implementation by using Reversible logic.[2] Reversible logic has less heat dissipating characteristics property with respect to irreversible gate. Also, Reversible logic has ultra-low power characteristics feature. In recent past it has been proved that reversible gates can implement any Boolean function.

scholarly journals Low Power High Speed Ternary Content Addressable Memory

2019 ◽  
Vol 8 (2) ◽  
pp. 2454-2458
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Search Engine ◽  
High Speed ◽  
Supply Voltage ◽  
Content Addressable Memory ◽  
Ternary Content Addressable Memory

Compared to Binary Content Addressable Memory (BiCAM) there are many applications for Ternary Content Addressable Memory (TCAM) as a search engine. But TCAM consumes more power than BiCAM. So, the saving of TCAM power consumption is the main objective of numerous designs. Precharge phase of the TCAM leads to more power consumption. Newly, a precharge free NOR type BiCAM has been suggested but it takes more time for its operation. Here, precharge free high speed NOR type TCAM is proposed. The proposed TCAM architecture takes power same as precharge free NOR type TCAM but its delay has been reduced by 84% . Simulations performed with cadence 45-nm technology at the supply voltage of 1V.

Low Energy Metric Content Addressable Memory (CAM) with Multi Voltage Matchline Segments

2015 ◽  
Vol 25 (02) ◽  
pp. 1650002 ◽  
Author(s):  
Mohammed V. Zackriya ◽  
Harish M. Kittur
Keyword(s):  
High Speed ◽  
Hardware Implementation ◽  
Clock Cycle ◽  
Process Variations ◽  
Lookup Table ◽  
Voltage Source ◽  
Switching Activity ◽  
Content Addressable Memory ◽  
Search Data ◽  
Search Speed

Content addressable memory (CAM) is a hardware implementation of lookup table which performs high speed search operation within a single clock cycle. Search data is compared in parallel with all the stored data and this increases switching activities as well as charging and discharging of capacitive matchlines (MLs). Here, we divide a wordline and ML into segments. For the first reported time the ML segments are precharged to different voltage levels to achieve improved energy metric. One of the segments associated with sub-ML is precharged with a low level of voltage source to reduce the power associated with ML activities. The main ML will discharge only when all the three segments match. Voltage scaling is done carefully in MLs where the switching activity is high to reduce the power consumption without degrading the search speed. A 256 [Formula: see text] 144 bit CAM is implemented with novel CAM cells in 45-nm technology node and the post-layout simulation is performed. The averaged energy metric is 0.12 fJ/search/bit for 625 Monte Carlo (MC) simulations with process variations.

scholarly journals Algorithmic TCAM on FPGA with data collision approach

2021 ◽  
Vol 22 (1) ◽  
pp. 89
Author(s):  
Nguyen Trinh ◽  
Anh Le Thi Kim ◽  
Hung Nguyen ◽  
Linh Tran
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Large Scale ◽  
Data Centers ◽  
Network Routing ◽  
Content Addressable Memory ◽  
Future Developments ◽  
Ternary Content Addressable Memory ◽  
Field Programmable ◽  
Data Collision

<span>Content addressable memory (CAM) and ternary content addressable memory (TCAM) are specialized high-speed memories for data searching. CAM and TCAM have many applications in network routing, packet forwarding and Internet data centers. These types of memories have drawbacks on power dissipation and area. As field-programmable gate array (FPGA) is recently being used for network acceleration applications, the demand to integrate TCAM and CAM on FPGA is increasing. Because most FPGAs do not support native TCAM and CAM hardware, methods of implementing algorithmic TCAM using FPGA resources have been proposed through recent years. Algorithmic TCAM on FPGA have the advantages of FPGAs low power consumption and high intergration scalability. This paper proposes a scaleable algorithmic TCAM design on FPGA. The design uses memory blocks to negate power dissipation issue and data collision to save area. The paper also presents a design of a 256 x 104-bit algorithmic TCAM on Intel FPGA Cyclone V, evaluates the performance and application ability of the design on large scale and in future developments.</span>

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