scholarly journals Algorithmic TCAM on FPGA with data collision approach

2021 ◽  
Vol 22 (1) ◽  
pp. 89
Author(s):  
Nguyen Trinh ◽  
Anh Le Thi Kim ◽  
Hung Nguyen ◽  
Linh Tran
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Large Scale ◽  
Data Centers ◽  
Network Routing ◽  
Content Addressable Memory ◽  
Future Developments ◽  
Ternary Content Addressable Memory ◽  
Field Programmable ◽  
Data Collision

<span>Content addressable memory (CAM) and ternary content addressable memory (TCAM) are specialized high-speed memories for data searching. CAM and TCAM have many applications in network routing, packet forwarding and Internet data centers. These types of memories have drawbacks on power dissipation and area. As field-programmable gate array (FPGA) is recently being used for network acceleration applications, the demand to integrate TCAM and CAM on FPGA is increasing. Because most FPGAs do not support native TCAM and CAM hardware, methods of implementing algorithmic TCAM using FPGA resources have been proposed through recent years. Algorithmic TCAM on FPGA have the advantages of FPGAs low power consumption and high intergration scalability. This paper proposes a scaleable algorithmic TCAM design on FPGA. The design uses memory blocks to negate power dissipation issue and data collision to save area. The paper also presents a design of a 256 x 104-bit algorithmic TCAM on Intel FPGA Cyclone V, evaluates the performance and application ability of the design on large scale and in future developments.</span>

scholarly journals Low Power Implementation Of Ternary Content Addressable Memory (TCAM)

2019 ◽  
Vol 9 (1S3) ◽  
pp. 455-460
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Clock Cycle ◽  
Reversible Logic ◽  
Ultra Low Power ◽  
Content Addressable Memory ◽  
Power Characteristics ◽  
Ternary Content Addressable Memory ◽  
Network Routers

In network routers, Ternary Content Addressable Memory (TCAM)[1] based search engines take an important role. One of the improved versions of Content Addressable Memory (CAM) is TCAM. For high speed and broader searching operation TCAM is used. Unlike normal CAM, TCAM has 3 logic states: 0, 1, ‘X’. In TCAM within one single clock cycle, search operation can be performed. That is why it is called special type of memory. Also, quick search ability is one of the popular features of TCAM. To compare the search and stored data, TCAM array acts parallel in every location. But high power dissipation is the main disadvantage of TCAM. To overcome this power dissipation in this paper we proposed a low power TCAM implementation by using Reversible logic.[2] Reversible logic has less heat dissipating characteristics property with respect to irreversible gate. Also, Reversible logic has ultra-low power characteristics feature. In recent past it has been proved that reversible gates can implement any Boolean function.

OPTIMIZED METHOD OF NETWORK PACKET ROUTING

2019 ◽  
pp. 27-32
Author(s):  
A. S. Kotlyarov
Keyword(s):  
High Speed ◽  
Large Scale ◽  
Data Transfer ◽  
Search Method ◽  
Concurrent Use ◽  
Parallel Pipeline ◽  
Field Programmable ◽  
Modified Block ◽  
Hardware Costs ◽  
Routing Tables

In the paper we review the possibility of using a block search method for network packets routing tasks in high-speed computer networks. The method provides minimization of hardware costs for large-scale routing tables. To support the maximum data transfer rate, it is necessary to perform real-time routing of packets. The existing solution presumes concurrent use of several routing devices. Each device performs independent search of records by the bisection method. However, if the channel rate exceeds 10 Gb/sec, and the number of routs exceeds 220, it leads to high hardware costs. To reduce hardware costs, we have suggested to use a modified block search method, which differs from the classic one by parallel-pipeline form of search. We have presented evaluation of the minimum field-programmable gate array hardware costs for the network packets routing task. Analysis of the results has proved efficiency of the suggested method in comparison with existing solutions. As a result, the hardware costs were reduced in 5 times.

EVALUATION STUDY OF SYSTOLIC ARRAY PROCESSORS OPTIMIZATION AND MAPPING ON k-LUT FPGA DEVICES

2013 ◽  
Vol 22 (04) ◽  
pp. 1350025
Author(s):  
STAVROS P. DOKOUZYANNIS ◽  
ARGIRIS P. MOKIOS
Keyword(s):  
Systolic Array ◽  
High Speed ◽  
Large Scale ◽  
Logic Synthesis ◽  
Evaluation Study ◽  
Optimization Approach ◽  
Array Processors ◽  
Field Programmable ◽  
High Level ◽  
Selection Of

This paper analyzes the design automation of embedded Systolic Array Processors (SAPs), into large scale Field Programmable Gate Array (FPGA) devices. SAPs are hardware implementations of a class of iterative, high-level language algorithms, for applications where the high-speed of processing has the principal meaning of a design. Embedding SAPs onto FPGAs is a complex process. The optimization phase in this process reduces the SAP significantly, thus less FPGA area is occupied by the embedded design, without any loss in the final performance. The present paper examines the effect of Projection Vectors (PVs) and Task Scheduling Vectors (TSVs) on the optimization process. Two optimization approaches are examined, namely technology mapping using FlowMap and Flowpack algorithms and optimization via logic synthesis using Xilinx Synthesis Tool. The multiplication of matrices, with entries being up to 32-bit integer vectors, has been taken as a sample space for the experiments conducted. The results, confirm that the selection of PV and TSV greatly affects the number of input/output signal connections of the FPGA, while the selection of an optimization approach affects the final number of logic resources occupied on the targeted device.

A Novel Low Power Technique for FinFET Domino OR Logic

2020 ◽  
pp. 2150117
Author(s):  
Kajal ◽  
Vijay Kumar Sharma
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Large Scale ◽  
Logic Gates ◽  
Leakage Power ◽  
Oxide Semiconductor ◽  
Domino Logic ◽  
Large Power ◽  
Leakage Reduction ◽  
The Impact

Excessive scaling of complementary metal oxide semiconductor (CMOS) technology is the main reason of large power dissipation in electronic circuits. Very large-scale integration (VLSI) industry has chosen an alternative option known as fin-shaped field effect transistor (FinFET) technology to mitigate the large power dissipation. FinFET is a multi-gate transistor which dissipates less leakage power as compared to CMOS transistors, but it does not completely resolve the problem of power dissipation. So, leakage reduction approaches are always required to mitigate the impact of power dissipation. In this paper, cascaded leakage control transistors (CLCT) leakage reduction technique is proposed using FinFET transistors. CLCT approach is tested for basic static logic circuits like inverter, 2-input NAND and NOR gates and compared with the existing leakage reduction techniques for leakage power dissipation and delay calculations at 16 and 14 nm technology nodes using Cadence tools. CLCT approach shows the effective reduction of leakage power with minimum delay penalty. As the domino logic gates are widely used in large memories and high-speed processors therefore, CLCT approach is further utilized for footless domino logic (FLDL) and compared with the available methods at 14[Formula: see text]nm technology node. CLCT approach reduces 35.16% power dissipation as compared to the conventional domino OR logic. Temperature and multiple parallel fin variations are estimated for the domino OR logic to check its reliable operation. CLCT approach has high-noise tolerance capability in term of unity noise gain (UNG) for domino OR logic as compared to the other methods.

scholarly journals Low Power High Speed Ternary Content Addressable Memory

2019 ◽  
Vol 8 (2) ◽  
pp. 2454-2458
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Search Engine ◽  
High Speed ◽  
Supply Voltage ◽  
Content Addressable Memory ◽  
Ternary Content Addressable Memory

Compared to Binary Content Addressable Memory (BiCAM) there are many applications for Ternary Content Addressable Memory (TCAM) as a search engine. But TCAM consumes more power than BiCAM. So, the saving of TCAM power consumption is the main objective of numerous designs. Precharge phase of the TCAM leads to more power consumption. Newly, a precharge free NOR type BiCAM has been suggested but it takes more time for its operation. Here, precharge free high speed NOR type TCAM is proposed. The proposed TCAM architecture takes power same as precharge free NOR type TCAM but its delay has been reduced by 84% . Simulations performed with cadence 45-nm technology at the supply voltage of 1V.

High-Speed Low-Power Bulk-Controlled Sense-Amplifier D Flip-Flop

2015 ◽  
Vol 713-715 ◽  
pp. 1042-1047
Author(s):  
Xiao Ying Deng ◽  
Yan Yan Mo ◽  
Jian Hui Ning
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Large Scale ◽  
Supply Voltage ◽  
Operating Conditions ◽  
Cmos Process ◽  
Flip Flop ◽  
Sense Amplifier ◽  
Operation Speed ◽  
Circuits Vlsi

With the development of digital very large scale integrated circuits (VLSI), how to reduce the power dissipation and improve the operation speed are two aspects among the most concerned fields. Based on sense amplifier technology and bulk-controlled technique, this paper proposes a bulk-controlled sense-amplifier D flip-flop (BCSADFF). Firstly, this flip-flop can change the threshold voltage of the NMOS by inputting control signals from the substrate so as to control the operating current. Secondly, the traditional RS flip-flop composed of two NAND gates is improved to a couple of inverters based on pseudo-PMOS dynamic technology. Therefore, the proposed BCSADFF can both effectively reduce the power dissipation and improve the circuit speed. Thirdly, the designed BCSADFF can work normally with ultra-dynamic voltage scaling from 1.8 V to 0.6V for SMIC 0.18-um standard CMOS process. Lastly, the Hspice simulation result shows that, compared with the traditional sense-amplifier D flip-flop (SADFF), the power dissipation of the BCSADFF is significantly reduced under the same operating conditions. When the power supply voltage is 0.9V, the power dissipation and delay of the SADFF is 6.54uW and 0.386ns while that of the proposed BCSADFF is 2.09uW and 0.237ns.

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